Data Sheet AD420
Rev. I | Page 7 of 16
TIMING REQUIREMENTS
T
A
= −40°C to +85°C, V
CC
= +12 V to +32 V.
THREE-WIRE INTERFACE
CLOCK
DATA IN
LATCH
DATA OUT
CLOCK
DATA IN
LATCH
DATA OUT
WORD “N” WORD “N + 1”
WORD “N – 1” WORD “N”
1011001 1 100 1111100 00
1101
(MSB)
B15
(LSB)
B15
B14
B13
B12
B14
B13
B12
B11
B10
B14
B15
B13
B12
B8
B7
B3
B2
B1
B0
B9
B5
B4
B6
t
CK
t
CL
t
CH
t
DW
t
LD
t
LL
t
LH
t
SD
t
DS
t
DH
00494-003
Figure 3. Timing Diagram for 3-Wire Interface
Table 5. Timing Specification for 3-Wire Interface
Parameter Label Limit Units
Data Clock Period t
CK
300 ns min
Data Clock Low Time t
CL
80 ns min
Data Clock High Time t
CH
80 ns min
Data Stable Width t
DW
125 ns min
Data Setup Time t
DS
40 ns min
Data Hold Time t
DH
5 ns min
Latch Delay Time t
LD
80 ns min
Latch Low Time t
LL
80 ns min
Latch High Time t
LH
80 ns min
Serial Output Delay Time t
SD
225 ns max
Clear Pulse Width t
CLR
50 ns min
THREE-WIRE INTERFACE FAST EDGES ON DIGITAL
INPUT
With a fast rising edge (<100 ns) on one of the serial inputs
(CLOCK, DATA IN, LATCH) while another input is logic high,
the part may be triggered into a test mode and the contents of
the data register may become corrupted, which may result in
the output being loaded with an incorrect value. If fast edges are
expected on the digital input lines, it is recommended that the
latch line remain at Logic 0 during serial loading of the DAC.
Similarly, the clock line should remain low during updates of
the DAC via the latch pin. Alternatively, the addition of small
value capacitors on the digital lines will slow down the edge.
CLOCK
DATA IN
CLOCK
DATA IN
(INTERNALLY GENERATED LATCH)
EXPANDED TIME VIEW BELOW
CLOCK COUNTER STARTS HERE
CONFIRM START BIT
SAMPLE BIT 15
START BIT
DATA BIT 15
BIT 14
EXPANDED TIME VIEW BELOW
CLOCK
DATA IN
01
012 8 16 24
001
START
BIT
STOP
BIT
NEXT
START
BIT
BIT13
TO BIT1
BIT15
BIT14
BIT0
t
ADW
t
ADS
t
ADH
t
ACH
t
ACL
t
ACK
00494-004
Figure 4. Timing Diagram for Asynchronous Interface
Table 6. Timing Specifications for Asynchronous Interface
Parameter Label Limit Units
Asynchronous Clock Period t
ACK
400 ns min
Asynchronous Clock Low Time t
ACL
50 ns min
Asynchronous Clock High Time t
ACH
150 ns min
Data Stable Width (Critical Clock Edge) t
ADW
300 ns min
Data Setup Time (Critical Clock Edge) t
ADS
60 ns min
Data Hold Time (Critical Clock Edge) t
ADH
20 ns min
Clear Pulse Width t
CLR
50 ns min
ASYNCHRONOUS INTERFACE
Note that in the timing diagram for asynchronous mode oper-
ation each data word is framed by a START (0) bit and a STOP
(1) bit. The data timing is with respect to the rising edge of the
CLOCK at the center of each bit cell. Bit cells are 16 clocks
long, and the first cell (the START bit) begins at the first clock
following the leading (falling) edge of the START bit. Thus, the
MSB (D15) is sampled 24 clock cycles after the beginning of
the START bit, D14 is sampled at clock number 40, and so on.
During any dead time before writing the next word the DATA
IN pin must remain at Logic 1.
The DAC output updates when the STOP bit is received. In
the case of a framing error (the STOP bit sampled as a 0) the
AD420 will output a pulse at the DATA OUT pin one clock
period wide during the clock period subsequent to sampling
the STOP bit. The DAC output will not update if a framing
error is detected.
