9FGV1001B004NBGI Datasheet 9FGV1001B001NBGI, 9FGV1001B004NBGI, 9FGV1001B003NBGI | P1-P3

Description

The 9FGV1001 is a member of IDT's PhiClock™ programmable

clock generator family. The 9FGV1001 provides four non-spread

spectrum copies of a single output frequency and two copies of

the crystal reference input. Two select pins allow for hardware

selection of the desired configuration, or two I

C bits allow easy

software selection of the desired configuration. The user may

configure any one of the four OTP configurations as the default

when operating in I

C mode. Four unique I

C addresses are

available, allowing easy I

C access to multiple components.

Typical Applications

▪ HPC

▪ Storage

▪ 10G/25G Ethernet

▪ Fiber Optic Modules

▪ SSDs

Output Features

▪ 4 programmable output pairs plus 2 LVCMOS REF outputs

▪ 1 integer output frequency per configuration

▪ 10MHz–325MHz output frequency (LVDS or LP-HCSL output

configuration)

▪ 10MHz–200MHz output frequency (LVCMOS output

configuration)

Features

▪ 1.8V–3.3V core V

and V

DDREF

▪ Individual 1.8V–3.3V V

DDO

for each programmable output pair

▪ Supports HCSL, LVDS and LVCMOS I/O standards

▪ Supports LVPECL and CML logic with easy AC coupling – see

application note AN-891

for alternate terminations

▪ HCSL utilizes IDT's LP-HCSL technology for improved

performance, lower power and higher integration:

• Programmable output impedance of 85 or 100Ω

▪ On-board OTP supports up to 4 complete configurations

▪ Configuration selected via strapping pins or I

▪ < 125mW at 1.8V, < 230mW at 3.3V with outputs running at

100MHz

▪ 4 programmable I

C addresses: D0/D1, D2/D3, D4/D5, D6/D7

read/write

▪ Supported by IDT Timing Commander™ software

▪ 4 × 4 mm 24-VFQFPN; minimal board space

Key Specifications

▪ 259fs rms typical phase jitter outputs at 156.25MHz (12kHz–

20MHz)

▪ PCIe Gen1–4 compliant

PCIe Clocking Architectures

Supported

▪ Common Clocked (CC)

▪ Independent Reference without spread spectrum (SRnS)

Block Diagram

REF1

REF0

OUT3#

^SEL1/SDA

Factory

Configuration

SMBus

Engine

INT

PLL

VDDREFp

XIN/CLKIN

VDDDp VDDAp

^OEA

^SEL0/SCL

OUT3

OUT0

OUT0#

Control Logic

^OEB

vSEL_I2C#

EPAD/GND

Internal terminations are available when LP -HCSL output format is selected .

OSC

VDDO3

OTP_VPP

INT

DIV

OUT2#

OUT2

OUT1#

OUT1

VDDO2

VDDO1

VDDO0

9FGV1001

Datasheet

Low Phase-Noise, Low-Power

Programmable PhiClock™ Generator

9FGV1001 Datasheet

Pin Assignments

Figure 1. Pin Assignments for 4 x 4 mm 24-VFQFPN Package – Top View

Pin Descriptions

Table 1. OE Mapping

OE[B:A] OUT0 OUT1 OUT2 OUT3 REF0 REF1

00 Running Stopped Stopped Stopped Running Running

01 Running Running Stopped Stopped Running Running

10 Running Running Running Stopped Running Running

11 Running Running Running Running Running Running

VDDREFp

vREF0_SEL_I2C#

VDDAp

VDDO3

OUT3#

OUT3

24 23 22 21 20 19

XIN/CLKIN 1

VDDO2

XO 2

OUT2

REF1 3

OUT2#

^SEL0/SCL 4

VDDO1

^SEL1/SDA 5

OUT1

^OEA 6

OUT1#

789101112

VDDDp

^OEB

OTP_VPP

OUT0#

OUT0

VDDO0

Note: The order of OUT3 is reversed from OUT[0:2]

^ prefix indicates internal pull-up resistor

v prefix indicates internal pull-down resistor

9FGV1001

connect

EPAD to GND

4 × 4 mm 24-VFQFPN, 0.5mm pitch

Table 2. Pin Descriptions

Number Name Type Description

1 XIN/CLKIN Input Crystal input or reference clock input.

2 XO Output Crystal output.

3 REF1 Output LVCMOS reference output.

4 ^SEL0/SCL Input

Select pin for internal frequency configurations/I

C clock pin. Function is determined by

state of SEL_I2C# upon power-up. This pin has an internal pull-up.

5 ^SEL1/SDA I/O

Select pin for internal frequency configurations/I

C data pin. Function is determined by state

of SEL_I2C# upon power-up. This pin has an internal pull-up.

6 ^OEA Input

Active high input for enabling outputs. This pin has an internal pull-up resistor.

0 = disable outputs, 1 = enable outputs.

9FGV1001 Datasheet

Note: Unused outputs can be programmed off and left floating. V

DDREF

and V

DDO0

have to be connected.

DDDp

Power

Digital power. 1.8V to 3.3V. V

DDAp

and V

DDDp

should be connected to the same power

supply.

8 ^OEB Input

Active high input for enabling outputs. This pin has an internal pull-up resistor.

0 = disable outputs, 1 = enable outputs.

9OTP_VPP Power

Voltage for programming OTP. During normal operation, this pin should be connected to the

same power rail as V

DDD

10 OUT0# Output Complementary output clock 0.

11 OUT0 Output Output clock 0.

12 V

DDO0

Power Power supply for output 0.

13 OUT1# Output Complementary output clock 1.

14 OUT1 Output Output clock 1.

15 V

DDO1

Power Power supply for output 1.

16 OUT2# Output Complementary output clock 2.

17 OUT2 Output Output clock 2.

18 V

DDO2

Power Power supply for output 2.

19 OUT3 Output Output clock 3.

20 OUT3# Output Complementary output clock 3.

21 V

DDO3

Power Power supply for output 3.

22 V

DDAp

Power

Power supply for analog circuits. V

DDAp

and V

DDDp

should be connected to the same power

supply. Programmable for nominal voltages of 1.8V, 2.5V or 3.3V.

23 vREF0_SEL_I2C#

Latched

I/O

Latched input/LVCMOS output. At power-up, the state of this pin is latched to select the

state of the I

C pins. After power-up, the pin acts as an LVCMOS reference output. This pin

has an internal pull-down.

1 = SEL0/SEL1.

0 = SCL/SDA.

24 V

DDREFp

Power Power supply for REF0 and REF1 and the internal XO. Programmable to 1.8V, 2.5V or 3.3V.

25 EPAD GND Connect to ground.

Table 2. Pin Descriptions (Cont.)

Number Name Type Description

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15

9FGV1001B004NBGI

Mfr. #:

Buy 9FGV1001B004NBGI

Manufacturer:

IDT

Description:

Clock Generators & Support Products 4 O/P 1INT PHI CLOCK

Lifecycle:

New from this manufacturer.

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9FGV1001B004NBGI

9FGV1001B004NBGI

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