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ADF4218LBRUZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
a
ADF4217L/ADF4218L/ADF4219L
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.
REV. C
Dual Low Power
Frequency Synthesizers
FUNCTIONAL BLOCK DIAGRAM
N = BP + A
11(13)-BIT IF
B COUNTER
6(5)-BIT IF
A COUNTER
IF
PRESCALER
OUTPUT
MUX
IF
LOCK
DETECT
CHARGE
PUMP
RF
LOCK
DETECT
CHARGE
PUMP
14(15)-BIT RF
R COUNTER
14(15)-BIT IF
R COUNTER
BUFFER
22-BIT
DATA
REGISTER
SDOUT
N = BP + A
11(13)-BIT RF
B COUNTER
6(5)-BIT RF
A COUNTER
RF
PRESCALER
PHASE
COMPARATOR
PHASE
COMPARATOR
ADF4217L/
ADF4218L/
ADF4219L
V
P
2V
P
1V
DD
2V
DD
1
ADF4219L ONLY
NC
IF
IN
A
IF
IN
B
ADF4217L
ADF4218L
ONLY
REF
IN
CLOCK
DATA
LE
RF
IN
A
RF
IN
B
DGND
RF
AGND
RF
DGND
IF
AGND
IF
CP
RF
MUXOUT
CP
IF
FEATURES IN ( ) REFER TO ADF4219L
NC = NO CONNECT
FEATURES
Total I
DD
: 7.1 mA
Bandwidth/RF 3.0 GHz
ADF4217L/ADF4218L, IF 1.1 GHz
ADF4219L, IF 1.0 GHz
2.6 V to 3.3 V Power Supply
1.8 V Logic Compatibility
Separate V
P
Allows Extended Tuning Voltage
Selectable Dual Modulus Prescaler
Selectable Charge Pump Currents
Charge Pump Current Matching of 1%
3-Wire Serial Interface
Power-Down Mode
APPLICATIONS
Wireless Handsets (GSM, PCS, DCS, CDMA, WCDMA)
Base Stations for Wireless Radio (GSM, PCS, DCS, WCDMA)
Wireless LANs
Communications Test Equipment
Cable TV Tuners (CATV)
GENERAL DESCRIPTION
The ADF4217L/ADF4218L/ADF4219L are low power dual
frequency synthesizers that can be used to implement local
oscillators in the up-conversion and down-conversion sections
of wireless receivers and transmitters. They can provide the LO
for both the RF and IF sections. They consist of a low noise
digital PFD (phase frequency detector), a precision charge pump,
a
programmable reference divider, programmable A and B counters,
and a dual modulus prescaler (P/P + 1). The A and B counters,
in conjunction with the dual modulus prescaler
(P/P + 1),
implement an N divider (N = BP + A). In addition, the 14-bit
reference counter (R Counter) allows selectable REFIN
fre-
quencies at the PFD input. A complete PLL (phase-locked
loop) can be implemented if the synthesizers are used with an
external loop filter and VCOs (voltage controlled oscillators).
Control of all the on-chip registers is via a simple 3-wire interface
with 1.8 V compatibility. The devices operate with a power supply
ranging from 2.6 V to 3.3 V and can be powered down when
not in use.
REV. C
–2–
ADF4217L/ADF4218L/ADF4219L–SPECIFICATIONS
1
(V
DD
1
= V
DD
2
= 2.6 V to 3.3 V; V
P
1, V
P
2 = V
DD
to 5.5 V; AGND = DGND = 0 V; T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
BChips
2
Parameter B Version
1
(T ypical) U nit Test Conditions/Comments
RF CHARACTERISTICS Use a square wave for operation
below minimum frequency spec.
RF Input Frequency (RF
IN
)
ADF4217L, ADF4218L 0.15/3.0 0.15/3.0 GHz min/max –10 dBm minimum input signal
ADF4217L, ADF4218L 0.15/2.5 0.15/2.5 GHz min/max –15 dBm minimum input signal
ADF4219L 0.8/2.2 0.8/2.2 GHz min/max –20 dBm minimum input signal
RF Input Sensitivity
ADF4217L, ADF4218L –15/0 –15/0 dBm min/max
ADF4219L –20/0 –20/0 dBm min/max
IF Input Frequency (IF
IN
)
ADF4217L/ADF4218L 0.045/1.1 0.045/1.1 GHz min/max –15 dBm minimum input signal
ADF4219L P = 16/17 0.045/1.0 0.045/1.0 GHz min/max –10 dBm minimum input signal
ADF4219L P = 8/9 0.045/0.55 0.045/0.55 GHz min/max –10 dBm minimum input signal
IF Input Sensitivity –15/0 –15/0 dBm min/max
Maximum Allowable Prescaler
Output Frequency
3
188 188 MHz max
REFIN CHARACTERISTICS
Reference Input Frequency 10/110 10/110 MHz min/max For f < 10 MHz, use dc-coupled
square wave, (0 to V
DD
).
Reference Input Sensitivity 0.5 0.5 V p-p min AC-coupled. When dc-coupled,
0 to V
DD
max.
REFIN Input Capacitance 10 10 pF max (CMOS compatible)
REFIN Input Current ± 100 ± 100 µA max
PHASE DETECTOR
Phase Detector Frequency
4
56 56 MHz max
CHARGE PUMP
I
CP
Sink/Source
High Value 4 4 mA typ
Low Value 1 1 mA typ
Absolute Accuracy 1 1 % typ
I
CP
Three-State Leakage Current 1 1 nA typ
Sink and Source Current Matching 6 6 % max 0.5 V < V
CP
< V
P
– 0.5, 1% typ
I
CP
vs. V
CP
55% max 0.5 V < V
CP
< V
P
– 0.5, 0.1% typ
I
CP
vs. Temperature 2 2 % typ V
CP
= V
P
/2
LOGIC INPUTS
V
INH
, Input High Voltage 1.4 1.4 V min
V
INL
, Input Low Voltage 0.6 0.6 V max
I
INH
/I
INL
, Input Current ± 1 ± 1 µA max
C
IN
, Input Capacitance 10 10 pF max
Reference Input Current ± 100 ± 100 µA max
LOGIC OUTPUTS
V
OH
, Output High Voltage V
DD
– 0.4 V
DD
– 0.4 V min I
OH
= 1 mA
V
OL
, Output Low Voltage 0.4 0.4 V max I
OL
= 1 mA
POWER SUPPLIES
V
DD
1 2.6/3.3 2.6/3.3 V min/V max
V
DD
2V
DD
1V
DD
1
V
P
1, V
P
2V
DD
1/5.5 V V
DD
1/5.5 V V min/V max
I
DD
(RF + IF)
5
10 10 mA max 7.1 mA typ
(RF only)
5
77mA 4.7 mA typ
(IF only)
5
55mA 3.4 mA typ
I
P
(I
P
1 + I
P
2) 0.6 0.6 mA typ T
A
= 25°C
Low Power Sleep Mode 1 1 µA typ
REV. C
–3–
ADF4217L/ADF4218L/ADF4219L
CLOCK
DATA
LE
LE
t
3
t
1
t
2
t
4
t
5
t
6
DB21 (MSB) DB20 DB2
DB1
(CONTROL BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
Figure 1. Timing Diagram
BChips
2
Parameter B Version
1
(T ypi c al) U nit Test Conditions/Comments
NOISE CHARACTERISTICS
6
RF Phase Noise Floor
7
–171 –171 dBc/Hz typ @ 30 kHz PFD Frequency
–163 –163 dBc/Hz typ @ 200 kHz PFD Frequency
IF Phase Noise Floor
7
–167 –167 dBc/Hz typ @ 30 kHz PFD Frequency
–159 –159 dBc/Hz typ @ 200 kHz PFD Frequency
Phase Noise Performance
8
@ VCO Output
RF
9
–75 –75 dBc/Hz typ 1.95 GHz Output; 30 kHz PFD
RF
10
–90 –90 dBc/Hz typ 900 MHz Output; 200 kHz PFD
IF
11
–77 –77 dBc/Hz typ 900 MHz Output; 30 kHz PFD
IF
12
–86 –86 dBc/Hz typ 900 MHz Output; 200 kHz PFD
Spurious Signals Measured at Offset of f
PFD
/2f
PFD
RF
9
–78/–85 –78/–85 dBc typ
RF
10
–80/–84 –80/–84 dBc typ
IF
11
–79/–86 –79/–86 dBc typ
IF
12
–80/–84 –80/–84 dBc typ
NOTES
1
Operating temperature range is as follows: B Version: –40°C to +85°C.
2
The BChip specifications are given as typical values.
3
This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency
that is less than this value.
4
Guaranteed by design. Sample tested to ensure compliance.
5
This includes relevant I
P
.
6
V
DD
= 3 V; P = 16/32; IF
IN
/RF
IN
for ADF4218L, ADF4219L = 540 MHz/900 MHz.
7
The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N divider value).
8
The phase noise is measured with the EVAL-ADF421xEB1 Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN
for the synthesizer. (f
REFOUT
= 10 MHz @ 0 dBm.)
9
f
REFIN
= 10 MHz; f
PFD
= 30 kHz; Offset frequency = 1 kHz; f
RF
= 1.95 GHz; N = 65000; Loop B/W = 3 kHz
10
f
REFIN
= 10 MHz; f
PFD
= 200 kHz; Offset frequency = 1 kHz; f
RF
= 900 MHz; N = 4500; Loop B/W = 20 kHz
11
f
REFIN
= 10 MHz; f
PFD
= 30 kHz; Offset frequency = 1 kHz; f
IF
= 900 MHz; N = 30000; Loop B/W = 3 kHz
12
f
REFIN
= 10 MHz; f
PFD
= 200 kHz; Offset frequency = 1 kHz; f
IF
= 900 MHz; N = 4500; Loop B/W = 20 kHz
Specifications subject to change without notice.
Limit at
T
MIN
to T
MAX
Parameter (B Version) Unit Test Conditions/Comments
t
1
10 ns min DATA to CLOCK Setup Time
t
2
10 ns min DATA to CLOCK Hold Time
t
3
25 ns min CLOCK High Duration
t
4
25 ns min CLOCK Low Duration
t
5
10 ns min CLOCK to LE Setup Time
t
6
50 ns min LE Pulsewidth
Guaranteed by design but not production tested.
TIMING CHARACTERISTICS
(V
DD
1 = V
DD
2 = 3 V ⴞ 10%, 5 V ⴞ 10%; V
DD
1, V
DD
2 ≤ V
P
1,
V
P
2 ≤ 6.0 V
; AGND
RF1
= DGND
RF1
= AGND
RF2
= DGND
RF2
= 0 V; T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24

ADF4218LBRUZ

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Buy ADF4218LBRUZ
Manufacturer:
Analog Devices Inc.
Description:
Phase Locked Loops - PLL Low Power Dual RF/IF Integer-N
Lifecycle:
New from this manufacturer.
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