OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

ADF4218LBRUZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
REV. C
ADF4217L/ADF4218L/ADF4219L
–4–
ABSOLUTE MAXIMUM RATINGS
1, 2
(
T
A
= 25°C, unless otherwise noted.)
V
DD
1 to GND
3
. . . . . . . . . . . . . . . . . . . . . . –0.3 V to +3.6 V
V
DD
1 to V
DD
2 . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
V
P
1, V
P
2 to GND . . . . . . . . . . . . . . . . . . . . –0.3 V to +5.8 V
V
P
1, V
P
2 to V
DD
1 . . . . . . . . . . . . . . . . . . . . –0.3 V to +5.5 V
Digital I/O Voltage to GND . . . . . . . . –0.3 V to V
DD
+ 0.3 V
Analog I/O Voltage to GND . . . . . . . . . –0.3 V to V
P
+ 0.3 V
REF
IN
, RF1
IN
(A, B), IF
IN
(A, B)
to GND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
RF
IN
A to RF
IN
B . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 320 mV
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . 150°C
TSSOP ␪
JA
Thermal Impedance . . . . . . . . . . . . . 150.4°C/W
LGA ␪
JA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112°C/W
Lead Temperature, Soldering
TSSOP, Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . 215°C
TSSOP, Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . 220°C
LGA, Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . 240°C
LGA, Infrared (20 sec) . . . . . . . . . . . . . . . . . . . . . . . 240°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause
perma-
nent damage to the device. This is a stress rating only; functional operation
of the
device at these or any other conditions above those listed in the operational
sections
of this specification is not implied. Exposure to absolute maximum rating
conditions
for extended periods may affect device reliability.
2
This device is a high performance RF integrated circuit with an ESD rating of
< 2 kV and is ESD sensitive. Proper precautions should be taken for handling
and
assembly.
3
GND = AGND = DGND = 0 V.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate
on the human body and test equipment and can discharge without detection. Although the ADF4217L/
ADF4218L/ADF4219L feature proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
ORDERING GUIDE
Temperature Package Package
Model Range Description Option
*
ADF4217L/ADF4218L/ADF4219LBRU –40°C to +85°CThin Shrink Small Outline Package (TSSOP) RU-20
ADF4217L/ADF4218L/ADF4219LBCC –40°C to +85°CChip Array CASON (LGA) CC-24
*Contact the factory for chip availability.
REV. C
ADF4217L/ADF4218L/ADF4219L
–5–
TSSOP
REF
IN
CLK
DATA
LE
MUXOUT
RF
IN
A
CP
RF
AGND
RF
RF
IN
B
V
DD
1
DGND
RF
V
DD
2
V
P
1
ADF4217L/
ADF4218L
DGND
IF
IF
INB
IF
INA
DGND
IF
CP
IF
V
P
2
1
10
11
20
AGND
IF
2
3
4
5
6
7
8
9
12
13
14
15
16
17
18
19
CHIP SCALE
REF
IN
CLK
MUXOUT
DGND
IF
10
DATA
LE
RF
IN
A
CP
RF
1
9
AGND
RF
RF
IN
B
V
DD
1
DGND
RF
V
DD
2
V
P
1
ADF4217L/
ADF4218L
AGND
IF
IF
IN
A
DGND
IF
CP
IF
V
P
2
21
13
24
NC
NCNC
NC
IF
IN
B
2
3
4
5
6
7
8
11 12
23 22
20
19
18
17
16
15
14
NC = NO INTERNAL CONNECT
TSSOP
REF
IN
CLK
DATA
LE
MUXOUT
RF
IN
A
CP
RF
AGND
RF
RF
IN
B
V
DD
1
DGND
RF
V
DD
2
V
P
1
ADF4219L
DGND
IF
AGND
IF
IF
IN
DGND
IF
CP
IF
V
P
2
1
10
11
20
NC
2
3
4
5
6
7
8
9
12
13
14
15
16
17
18
19
CHIP SCALE
REF
IN
CLK
MUXOUT
DGND
IF
10
DATA
LE
RF
IN
A
CP
RF
1
9
AGND
RF
RF
IN
B
V
DD
1
DGND
RF
V
DD
2
V
P
1
ADF4219L
NC
IF
IN
DGND
IF
CP
IF
V
P
2
21
13
24
NC
NC
NC
NC
AGND
IF
2
3
4
5
6
7
8
11 12
23 22
20
19
18
17
16
15
14
NC = NO INTERNAL CONNECT
PIN CONFIGURATIONS
REV. C
ADF4217L/ADF4218L/ADF4219L
–6–
PIN FUNCTION DESCRIPTIONS
Mnemonic Function
V
DD
1Positive Power Supply for the RF Section. Decoupling capacitors to the analog ground plane should be placed as
close as possible to this pin. V
DD
1 should have a value of between 2.6 V and 3.3 V. V
DD
1 must have the same
potential as V
DD
2.
V
P
1Power Supply for the RF Charge Pump. This should be greater than or equal to V
DD
.
CP
RF
Output from the RF Charge Pump. When enabled, this provides ±I
CP
to the external loop filter, which in turn
drives the external VCO.
DGND
RF
Ground Pin for the RF Digital Circuitry
RF
IN
A Input to the RF Prescaler. This low level input signal is normally ac-coupled to the external VCO.
RF
IN
BComplementary Input to the RF Prescaler. This point should be decoupled to the ground plane with a small
bypass capacitor, typically 100 pF.
AGND
RF
Ground Pin for the RF Analog Circuitry
REF
IN
Reference Input. This is a CMOS input with a nominal threshold of V
DD
/2 and an equivalent input resistance of
100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator, or can be ac-coupled.
DGND
IF
Ground Pin for the IF Digital, Interface, and Control Circuitry
MUXOUT This multiplexer output allows either the IF/RF Lock Detect, the scaled RF, or the scaled Reference Frequency to
be accessed externally (Table V).
CLK Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the
22-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.
DATA Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is a
high impedance CMOS input.
LE Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four
latches; the latch is selected using the control bits.
AGND
IF
Ground Pin for the IF Analog Circuitry
NC This pin is not connected internally (ADF4219L only).
IF
IN
BComplementary Input to the IF Prescaler. This point should be decoupled to the ground plane with a small bypass
capacitor, typically 100 pF (ADF4217L/ADF4218L only).
IF
IN
A Input to the IF Prescaler. This low level input signal is normally ac-coupled to the external VCO.
DGND
IF
Ground Pin for the IF Digital, Interface, and Control Circuitry
CP
IF
Output from the IF Charge Pump. When enabled, this provides ±I
CP
to the external loop filter, which in turn drives
the external VCO.
V
P
2Power Supply for the IF Charge Pump. This should be greater than or equal to V
DD
.
V
DD
2Positive Power Supply for the IF Interface and Oscillator Sections. Decoupling capacitors to the analog ground
plane should be placed as close as possible to this pin. V
DD
2 should have a value of between 2.6 V and 3.3 V.
V
DD
2 must have the same potential as V
DD
1.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24

ADF4218LBRUZ

Mfr. #:
Buy ADF4218LBRUZ
Manufacturer:
Analog Devices Inc.
Description:
Phase Locked Loops - PLL Low Power Dual RF/IF Integer-N
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet