OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

954201BFLFT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
ICS954201
0819H—02/17/06
Pin Configuration
Recommended Application:
CK410M clock, Intel Yellow Cover part
Output Features:
• 2 - 0.7V current-mode differential CPU pairs
• 7 - 0.7V current-mode differential SRC pair for SATA and
PCI-E
• 1 - 0.7V current-mode differential CPU/SRC selectable
pair
• 4 - PCI (33MHz)
• 2 - PCICLK_F, (33MHz) free-running
• 1 - USB, 48MHz
• 1 - DOT, 96MHz, 0.7V current differential pair
• 1 - REF, 14.318MHz
Key Specifications:
• CPU outputs cycle-cycle jitter < 85ps
• SRC outputs cycle-cycle jitter < 125ps
• PCI outputs cycle-cycle jitter < 500ps
• +/- 300ppm frequency accuracy on CPU & SRC clocks
• +/- 100ppm frequency accuracy on USB clocks
Programmable Timing Control Hub™ for Mobile P4™ Systems
Functionality
Features/Benefits:
• Supports tight ppm accuracy clocks for Serial-ATA and
PCI-Express
• Supports spread spectrum modulation, 0 to -0.5%
down spread
• Supports CPU clocks up to 400MHz
• Uses external 14.318MHz crystal, external crystal load
caps are required for frequency tuning
• Supports undriven differential CPU, SRC pair in PD#
for power management.
56-pin SSOP & TSSOP
VDDPCI 1 56 PCICLK2
GND 2 55 PCI/SRC_STOP#
PCICLK3 3 54 CPU_STOP#
PCICLK4 4 53 FS_C/TEST_SEL
PCICLK5 5 52 REFOUT
GND 6 51 GND
VDDPCI 7 50 X1
ITP_EN/PCICLK_F0 8 49 X2
PCICLK_F1 9 48 VDDREF
Vtt_PwrGd#/PD 10 47 SDATA
VDD4811 46SCLK
USB_48MHz/FS_A 12 45 GND
GND 13 44 CPUCLKT0
DOTT_96MHz 14 43 CPUCLKC0
DOTC_96MHz 15 42 VDDCPU
FS_B/TEST_MODE 16 41 CPUCLKT1
SRCCLKT0 17 40 CPUCLKC1
SRCCLKC0 18 39 IREF
SRCCLKT1 19 38 GNDA
SRCCLKC1 20 37 VDDA
VDDSRC 21 36 CPUCLKT2_ITP/SRCCLKT7
SRCCLKT2 22 35 CPUCLKC2_ITP/SRCCLKC7
SRCCLKC2 23 34 VDDSRC
SRCCLKT3 24 33 SRCCLKT6
SRCCLKC3 25 32 SRCCLKC6
SRCCLKT4_SATA 26 31 SRCCLKT5
SRCCLKC4_SATA 27 30 SRCCLKC5
VDDSRC 28 29 GND
ICS954201
FS_C
1
FS_B
2
FS_A
2
CPU
MHz
SRC
MHz
PCI
MHz
REF
MHz
U
SB
MHz
DOT
MHz
0 0 0 266.66 100.00 33.33 14.318 48.00 96.00
0 0 1 133.33 100.00 33.33 14.318 48.00 96.00
0 1 0 200.00 100.00 33.33 14.318 48.00 96.00
0 1 1 166.66 100.00 33.33 14.318 48.00 96.00
1 0 0 333.33 100.00 33.33 14.318 48.00 96.00
1 0 1 100.00 100.00 33.33 14.318 48.00 96.00
1 1 0 400.00 100.00 33.33 14.318 48.00 96.00
1 1 1 14.318 48.00 96.00
1. FS_C is a three-level input. Please see V
IL_FS
and V
IH_FS
specifications in
the Input/Supply/Common Output Parameters Table for correct values.
Also refer to the Test Clarification Table.
2. FS_B and FS_A are low-threshold inputs. Please see the V
IL_FS
and V
IH_FS
specifications in the Input/Supply/Common Output Parameters Table for correct values.
RESERVED
2
ICS954201
0819H—02/17/06
Pin Description
PIN # PIN NAME
PIN
TYPE
DESCRIPTION
1 VDDPCI PWR Power supply for PCI clocks, nominal 3.3V
2 GND PWR Ground pin.
3 PCICLK3 OUT PCI clock output.
4 PCICLK4 OUT PCI clock output.
5 PCICLK5 OUT PCI clock output.
6 GND PWR Ground pin.
7 VDDPCI PWR Power supply for PCI clocks, nominal 3.3V
8 ITP_EN/PCICLK_F0 I/O
Free running PCI clock not affected by PCI_STOP#.
ITP_EN: latched input to select pin functionality
1 = CPU_ITP pair
0 = SRC pair
9 PCICLK_F1 OUT Free running PCI clock not affected by PCI_STOP# .
10 Vtt_PwrGd#/PD IN
Vtt_PwrGd# is an active low input used to determine when
latched inputs are ready to be sampled. PD is an asynchronous
active high input pin used to put the device into a low power
state. The internal clocks, PLLs and the crystal oscillator are
stopped.
11 VDD48 PWR Power pin for the 48MHz output.3.3V
12 USB_48MHz/FS_A I/O
Frequency select latch input pin / Fixed 48MHz USB clock
output. 3.3V.
13 GND PWR Ground pin.
14 DOTT_96MHz OUT True clock of differential pair for 96.00MHz DOT clock.
15 DOTC_96MHz OUT Complement clock of differential pair for 96.00MHz DOT clock.
16 FS_B/TEST_MODE IN
3.3V tolerant input for CPU frequency selection. Refer to input
electrical characteristics for Vil_FS and Vih_FS values.
TEST_MODE is a real time input to select between Hi-Z and
REF/N divider mode while in test mode. Refer to Test
Clarification Table.
17 SRCCLKT0 OUT True clock of differential SRC clock pair.
18 SRCCLKC0 OUT Complement clock of differential SRC clock pair.
19 SRCCLKT1 OUT True clock of differential SRC clock pair.
20 SRCCLKC1 OUT Complement clock of differential SRC clock pair.
21 VDDSRC PWR Supply for SRC clocks, 3.3V nominal
22 SRCCLKT2 OUT True clock of differential SRC clock pair.
23 SRCCLKC2 OUT Complement clock of differential SRC clock pair.
24 SRCCLKT3 OUT True clock of differential SRC clock pair.
25 SRCCLKC3 OUT Complement clock of differential SRC clock pair.
26 SRCCLKT4_SATA OUT True clock of differential SRC/SATA pair.
27 SRCCLKC4_SATA OUT Complement clock of differential SRC/SATA pair.
28 VDDSRC PWR Supply for SRC clocks, 3.3V nominal
3
ICS954201
0819H—02/17/06
Pin Description (Continued)
PIN
#
PIN NAME TYPE DESCRIPTION
29 GND PWR Ground pin.
30 SRCCLKC5 OUT Complement clock of differential SRC clock pair.
31 SRCCLKT5 OUT True clock of differential SRC clock pair.
32 SRCCLKC6 OUT Complement clock of differential SRC clock pair.
33 SRCCLKT6 OUT True clock of differential SRC clock pair.
34 VDDSRC PWR Supply for SRC clocks, 3.3V nominal
35 CPUCLKC2_ITP/SRCCLKC7 OUT
Complimentary clock of CPU_ITP/SRC differential pair
CPU_ITP/SRC output. These are current mode outputs.
External resistors are required for voltage bias. Selected by
ITP_EN input.
36 CPUCLKT2_ITP/SRCCLKT7 OUT
True clock of CPU_ITP/SRC differential pair CPU_ITP/SRC
output. These are current mode outputs. External resistors are
required for voltage bias. Selected by ITP_EN input.
37 VDDA PWR 3.3V power for the PLL core.
38 GNDA PWR Ground pin for the PLL core.
39 IREF OUT
This pin establishes the reference current for the differential
current-mode output pairs. This pin requires a fixed precision
resistor tied to ground in order to establish the appropriate
current. 475 ohms is the standard value.
40 CPUCLKC1 OUT
Complimentary clock of differential pair CPU outputs. These are
current mode outputs. External resistors are required for voltage
bias.
41 CPUCLKT1 OUT
True clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
42 VDDCPU PWR Supply for CPU clocks, 3.3V nominal
43 CPUCLKC0 OUT
Complimentary clock of differential pair CPU outputs. These are
current mode outputs. External resistors are required for voltage
bias.
44 CPUCLKT0 OUT
True clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
45 GND PWR Ground pin.
46 SCLK IN Clock pin of SMBus circuitry, 5V tolerant.
47 SDATA I/O Data pin for SMBus circuitry, 5V tolerant.
48 VDDREF PWR Ref, XTAL power supply, nominal 3.3V
49 X2 OUT Crystal output, Nominally 14.318MHz
50 X1 IN Crystal input, Nominally 14.318MHz.
51 GND PWR Ground pin.
52 REFOUT OUT Reference Clock output
53 FS_C/TEST_SEL IN
3.3V tolerant input for CPU frequency selection. Low voltage
threshold inputs, see input electrical characteristics for Vil_FS
and Vih_FS values.
TEST_Sel: 3-level latched input to enable test mode.
Refer to Test Clarification Table
54 CPU_STOP# IN Stops all CPUCLK, except those set to be free running clocks
55 PCI/SRC_STOP# IN
Stops all PCICLKs and SRCCLKs besides the free-running
clocks at logic 0 level, when input low
56 PCICLK2 OUT PCI clock output.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

954201BFLFT

Mfr. #:
Buy 954201BFLFT
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner PC MAIN CLOCK
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet