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954201BFLFT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
4
ICS954201
0819H—02/17/06
ICS954201 is a CK410M Yellow Cover clock synthesizer. ICS954201 provides a single-chip solution for mobile systems built
with Intel P4-M processors and Intel mobile chipsets. ICS954201 is driven with a 14.318MHz crystal and generates CPU
outputs up to 400MHz. It provides the tight ppm accuracy required by Serial ATA and PCI-Express.
General Description
Block Diagram
Power Groups
VDD GND
48 51 Xtal, Ref
1,7 2,6 PCICLK outputs
21,28,34 29 SRCCLK outputs
37 38 Master clock, CPU Analog
11 13 DOT, USB, PLL_48
42 45 CPUCLK clocks
Description
Pin Number
PROG.
SPREAD
MAIN PLL
PCICLK(5:2)
CONTROL
LOGIC
XTAL
OSC.
CPUCLK(1:0)
FIXED PLL
USB_48MHz
DIVIDER
PROG.
DIVIDERS
REF
SRCCLK(6:0)
ITP_EN
SDATA
SCLK
TEST_MODE
X1
X2
IREF
FS(C:A)
TEST_SEL
VTT_PWRGD#/PD
DOT_96MHz
PCICLK_F(1:0)
CPUCLK2_ITP/SRCCLK7
PCI/SRC_STOP#
CPU_STOP#
5
ICS954201
0819H—02/17/06
General I
2
C serial interface information for the ICS954201
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2
(H)
• ICS clock will
acknowledge
• Controller (host) sends the begining byte location = N
• ICS clock will
acknowledge
• Controller (host) sends the data byte count = X
• ICS clock will
acknowledge
• Controller (host) starts sending
Byte N through
Byte N + X -1
(see Note 2)
• ICS clock will
acknowledge
each byte
one at a time
• Controller (host) sends a Stop bit
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the write address D2
(H)
• ICS clock will
acknowledge
• Controller (host) sends the begining byte
location = N
• ICS clock will
acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address D3
(H)
• ICS clock will
acknowledge
• ICS clock will send the data byte count = X
• ICS clock sends
Byte N + X -1
• ICS clock sends
Byte 0 through byte X (if X
(H)
was written to byte 8)
.
• Controller (host) will need to acknowledge each byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
ICS (Slave/Receiver)
T
WR
ACK
ACK
ACK
ACK
ACK
PstoP bit
X Byte
Index Block Write Operation
Slave Address D2
(H)
Beginning Byte = N
WRite
starT bit
Controller (Host)
Byte N + X - 1
Data Byte Count = X
Beginning Byte N
T starT bit
WR WRite
RT Repeat starT
RD ReaD
Beginning Byte N
Byte N + X - 1
N Not acknowledge
PstoP bit
Slave Address D3
(H)
Index Block Read Operation
Slave Address D2
(H)
Beginning Byte = N
ACK
ACK
Data Byte Count = X
ACK
ICS (Slave/Receiver)
Controller (Host)
X Byte
ACK
ACK
6
ICS954201
0819H—02/17/06
Absolute Max
Symbol Parameter Min Max Units
VDD_A 3.3V Core Supply Voltage V
DD
+ 0.5V V
VDD_In 3.3V Logic Input Supply Voltage GND - 0.5 V
DD
+ 0.5V V
Ts Storage Temperature -65 150
°
C
Tambient Ambient Operating Temp 0 70 °C
Tcase Case Temperature 115 °C
ESD prot
Input ESD protection
human body model
2000 V
Electrical Characteristics - Input/Supply/Common Output Parameters
T
A
= 0 - 70°C; Supply Voltage V
DD
= 3.3 V +/-5%
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Notes
Input High Voltage V
IH
3.3 V +/-5% 2 V
DD
+ 0.3 V 1
Input Low Voltage V
IL
3.3 V +/-5% V
SS
- 0.3 0.8 V 1
Input High Current I
IH
V
IN
= V
DD
-5 5 uA 1
I
IL1
V
IN
= 0 V; Inputs with no pull-up
resistors
-5 uA 1
I
IL2
V
IN
= 0 V; Inputs with pull-up
resistors
-200 uA 1
Low Threshold Input High
Voltage
V
IH_FS
3.3 V +/-5% 0.7 V
DD
+ 0.3 V 1
Low Threshold Input Low
Voltage
V
IL_FS
3.3 V +/-5% V
SS
- 0.3 0.35 V 1
Operating Supply Current I
DD3. 3OP
Full Active, C
L
= Full load; 278 400 mA
all diff pairs driven 67 70 mA
all differential pairs tri-stated 4.8 12 mA
Input Frequency
3
F
i
V
DD
= 3.3 V 14.31818 MHz 3
Pin Inductance
1
L
p
in
7nH1
C
IN
Logic Inputs 5 pF 1
C
OUT
Output pin capacitance 6 pF 1
C
INX
X1 & X2 pins 5 pF 1
Clk Stabilization
1,2
T
STAB
From V
DD
Power-Up or de-
assertion of PD# to 1st clock
1.3 1.8 ms 1,2
Modulation Frequency Triangular Modulation 30 33 kHz 1
Tdrive_SRC
SRC output enable after
PCI_STOP de-assertion
810ns1
Tdrive_PD
Differential output enable after
PD# de-assertion
300 us 1
Tfall_PD PD# fall time of 5 ns 1
Trise_PD PD# rise time of 5 ns 2
Tdrive_CPU_STOP
CPU output enable after
CPU_STOP de-assertion
810ns1
Tfall_CPU_STOP CPU_STOP fall time of 5 ns 1
Trise_CPU_STOP# CPU_STOP rise time of 5 ns 2
SMBus Voltage V
DD
2.7 5.5 V 1
Low-level Output Voltage V
OL
SDATA, SCLK @ I
PULLUP
0.4 V 1
Current sinking I
PULLUP
V
OL
= 0.4 V 4 mA 1
SCLK/SDATA
Clock/Data Rise Time
T
RI2C
(Max VIL - 0.15) to
(Min VIH + 0.15)
1000 ns 1,3
SCLK/SDATA
Clock/Data Fall Time
T
FI2C
(Min VIH + 0.15) to
(Max VIL - 0.15)
300 ns 1,3
1
Guaranteed by design, not 100% tested in production.
2
See timing diagrams for timing requirements.
3
In
p
ut fre
q
uenc
y
should be measured at the REF out
p
ut
p
in and tuned to ideal 14.31818MHz to meet
Input Low Current
Powerdown Current I
DD3.3PD
Input Capacitance
1
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

954201BFLFT

Mfr. #:
Buy 954201BFLFT
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner PC MAIN CLOCK
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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