13
ICS954201
0819H—02/17/06
SMBus Table: Test and Readback Control Register
Pin
Name Control Function T
e0 1 PWD
Bit 7
Test Mode Selection Test Mode Selection RW Hi-Z REF/N 0
Bit 6
Test Clock Mod eEntr
Test Mode RW Disable Enable 0
Bit 5
0
Bit 4
REFOUT STRENGTH Strength Prog RW 1X 2X 1
Bit 3
PCI/SRC_STOP
Stop all PCI and SRC
clocks
RW Enabled Disabled 1
Bit 2
FS_C readback R - - LATCHED
Bit 1
FS_B readback R - - LATCHED
Bit 0
FS_A readback R - - LATCHED
SMBus Table: Vendor & Revision ID Register
Pin
Name Control Function T
e0 1 PWD
Bit 7
RID3 R - - 0
Bit 6
RID2 R - - 0
Bit 5
RID1 R - - 0
Bit 4
RID0 R - - 1
Bit 3
VID3 R - - 0
Bit 2
VID2 R - - 0
Bit 1
VID1 R - - 0
Bit 0
VID0 R - - 1
RESERVED
-
VENDOR ID
-
-
-
B
te 7
-
REVISION ID
-
-
-
-
-
-
-
-
-
-
-
B
te 6
Test Clarification Table
Comments
FS_C/TEST
_SEL
HW PIN
FS_B/TEST
_MODE
HW PIN
TEST
ENTRY
BIT
B6b6
REF/N or
HI-Z
B6b7 OUTPUT
0X0XNORMAL
10X0HI-Z
10X1REF/N
11X0REF/N
11X1REF/N
0X10HI-Z
0X11REF/N
B6b6: 1= ENTER TEST MODE, Default = 0 (NORMAL OPERATION)
B6b7: 1= REF/N, Default = 0 (HI-Z)
HW SW
· FS_C/TEST_SEL is a 3-level latched input.
o Power-up w/ V >= 2.0V to select TEST
o Power-up w/ V < 2.0V to have pin function as
FS_C.
· When pin is FS_C, VIH_FS and VIL_FS levels
apply.
· FS_B/TEST_MODE is a low-threshold input
o VIH_FS and VIL_FS levels apply.
o TEST_MODE is a real time input
· TEST_SEL can be invoked after power up
through SMBus B6b6.
o If TEST is selected by B6b6, only B6b7 controls
TEST_MODE. The FS_B/TEST_Mode pin is not
used.
· Power must be cycled to exit TEST.
