COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V261LA/72V271LA
3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9
10
SERIAL PROGRAMMING MODE
If Serial Programming mode has been selected, as described above,
then programming of PAE and PAF values can be achieved by using a
combination of the LD, SEN, WCLK and SI input pins. Programming
PAE and PAF proceeds as follows: when LD and SEN are set LOW,
data on the SI input are written, one bit for each WCLK rising edge,
starting with the Empty Offset LSB and ending with the Full Offset MSB.
A total of 28 bits for the IDT72V261LA and 30 bits for the IDT72V271LA.
See Figure 13, Serial Loading of Programmable Flag Registers, for the
timing diagram for this mode.
Using the serial method, individual registers cannot be programmed
selectively. PAE and PAF can show a valid status only after the com-
plete set of bits (for all offset registers) has been entered. The registers
can be reprogrammed as long as the complete set of new offset bits is
entered. When LD is LOW and SEN is HIGH, no serial write to the
registers can occur.
Write operations to the FIFO are allowed before and during the serial
programming sequence. In this case, the programming of all offset bits
does not have to occur at once. A select number of bits can be written
to the SI input and then, by bringing LD and SEN HIGH, data can be
written to FIFO memory via Dn by toggling WEN. When WEN is brought
HIGH with LD and SEN restored to a LOW, the next offset bit in se-
quence is written to the registers via SI. If an interruption of serial
programming is desired, it is sufficient either to set LD LOW and deacti-
vate SEN or to set SEN LOW and deactivate LD. Once LD and SEN
are both restored to a LOW level, serial offset programming continues.
From the time serial programming has begun, neither partial flag will
be valid until the full set of bits required to fill all the offset registers has
been written. Measuring from the rising WCLK edge that achieves the
above criteria; PAF will be valid after two more rising WCLK edges plus
tPAF, PAE will be valid after the next two rising RCLK edges plus tPAE
plus tSKEW2.
It is not possible to read the flag offset values in a serial mode.
PARALLEL MODE
If Parallel Programming mode has been selected, as described above,
then programming of PAE and PAF values can be achieved by using a
combination of the LD, WCLK , WEN and Dn input pins. For the
IDT72V261LA and the IDT72V271LA, programming PAE and PAF pro-
ceeds as follows: when LD and WEN are set LOW, data on the inputs
Dn are written into the Empty Offset LSB Register on the first LOW-to-
HIGH transition of WCLK. Upon the second LOW-to-HIGH transition of
WCLK, data are written into the Empty Offset MSB Register. Upon the
third LOW-to-HIGH transition of WCLK, data are written into the Full
Offset LSB Register. Upon the fourth LOW-to-HIGH transition of WCLK,
data are written into the Full Offset MSB Register. The fifth transition of
WCLK writes, once again, to the Empty Offset LSB Register. See Fig-
ure 14, Parallel Loading of Programmable Flag Registers for the
IDT72V261LA, for the timing diagram for this mode.
The act of writing offsets in parallel employs a dedicated write offset
register pointer. The act of reading offsets employs a dedicated read
offset register pointer. The two pointers operate independently; how-
ever, a read and a write should not be performed simultaneously to the
offset registers. A Master Reset initializes both pointers to the Empty
Offset (LSB) register. A Partial Reset has no effect on the position of
these pointers.
Write operations to the FIFO are allowed before and during the paral-
lel programming sequence. In this case, the programming of all offset
registers does not have to occur at one time. One, two or more offset
registers can be written and then by bringing LD HIGH, write operations
can be redirected to the FIFO memory. When LD is set LOW again,
and WEN is LOW, the next offset register in sequence is written to. As
an alternative to holding WEN LOW and toggling LD, parallel program-
ming can also be interrupted by setting LD LOW and toggling WEN.
Note that the status of a partial flag (PAE or PAF) output is invalid
during the programming process. From the time parallel programming
has begun, a partial flag output will not be valid until the appropriate
offset word has been written to the register(s) pertaining to that flag.
Measuring from the rising WCLK edge that achieves the above criteria;
PAF will be valid after two more rising WCLK edges plus tPAF, PAE will
be valid after the next two rising RCLK edges plus tPAE plus tSKEW2.
The act of reading the offset registers employs a dedicated read
offset register pointer. The contents of the offset registers can be read
on the Q0-Qn pins when LD is set LOW and REN is set LOW. For the
IDT72V261LA and IDT72V271LA, data are read via Qn from the Empty
Offset LSB Register on the first LOW-to-HIGH transition of RCLK. Upon
the second LOW-to-HIGH transition of RCLK, data are read from the
Empty Offset MSB Register. Upon the third LOW-to-HIGH transition of
RCLK, data are read from the Full Offset LSB Register. Upon the
fourth LOW-to-HIGH transition of RCLK, data are read from the Full
Offset MSB Register. The fifth transition of RCLK reads, once again,
from the Empty Offset LSB Register. See Figure 15, Parallel Read of
Programmable Flag Registers for the IDT72V261LA, for the timing dia-
gram for this mode.
It is permissible to interrupt the offset register read sequence with
reads or writes to the FIFO. The interruption is accomplished by
deasserting REN, LD, or both together. When REN and LD are restored
to a LOW level, reading of the offset registers continues where it left
off. It should be noted, and care should be taken from the fact that
when a parallel read of the flag offsets is performed, the data word that
was present on the output lines Qn will be overwritten.
Parallel reading of the offset registers is always permitted regardless
of which timing mode (IDT Standard or FWFT modes) has been se-
lected.
RETRANSMIT OPERATION
The Retransmit operation allows data that has already been read to
be accessed again. There are two stages: first, a setup procedure that
resets the read pointer to the first location of memory, then the actual
retransmit, which consists of reading out the memory contents, starting
at the beginning of memory.
Retransmit setup is initiated by holding RT LOW during a rising RCLK
edge. REN and WEN must be HIGH before bringing RT LOW. At least
one word, but no more than D - 2 words should have been written into
the FIFO between Reset (Master or Partial) and the time of Retransmit
setup. D = 16,384 for the IDT72V261LA and D = 32,768 for the
IDT72V271LA in IDT Standard mode. In FWFT mode, D = 16,385 for
the IDT72V261LA and D = 32,769 for the IDT72V271LA.
If IDT Standard mode is selected, the FIFO will mark the beginning of
the Retransmit setup by setting EF LOW. The change in level will only
be noticeable if EF was HIGH before setup. During this period, the
internal read pointer is initialized to the first location of the RAM array.
