LTC4257
10
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is designed to accept this thermal load and is thermally
protected to avoid damage to the onboard power MOSFET.
Note that the PD designer must ensure that the PD steady-
state power consumption falls within the limits shown in
Table 2.
Power Good
The LTC4257 includes a power good circuit (Figure 6) that
is used to indicate to the PD circuitry that load capacitor C1
is fully charged and that the PD can start DC/DC converter
operation. The power good circuit monitors the voltage
across the internal power MOSFET and PWRGD is as-
serted when the voltage drops below 1.5V. The power
good circuit includes a large amount of hysteresis to allow
the LTC4257 to operate near the current limit point without
inadvertently disabling PWRGD. The MOSFET voltage
must increase to 3V before PWRGD is disabled.
If a sudden increase in voltage appears on the input line,
this voltage step will be transferred through capacitor C1
and appear across the power MOSFET. The response of
the LTC4257 will depend on the magnitude of the voltage
step, the rise time of the step, the value of capacitor C1 and
the DC load. For fast rising inputs, the LTC4257 will
attempt to quickly charge capacitor C1 using an internal
secondary current limit circuit. In this scenario, the PSE
current limit should provide the overall limit for the circuit.
For slower rising inputs, the 350mA current limit in the
LTC4257 will set the charge rate of capacitor C1. In either
case, the PWRGD signal may go inactive briefly while the
capacitor is charged up to the new line voltage. In the
design of a PD, it is necessary to determine if a step in the
input voltage will cause the PWRGD signal to go inactive
and how to respond to this event. In some designs, the
charge on C1 is sufficient to power the PD through this
event. In this case, it may be desirable to filter the PWRGD
signal so that intermittent power bad conditions are
ignored. Figure 10 demonstrates methods to insert a
lowpass filter on the power good interface.
For PD designs that use a large load capacitor and also
consume a lot of power, it is important to delay activation
of the PD circuitry with the PWRGD signal. If the PD cir-
cuitry is not disabled during the current-limited turn-on se-
quence, the PD circuitry will rob current intended for charg-
ing up the load capacitor and create a slow rising input,
possibly causing the LTC4257 to go into thermal shutdown.
The PWRGD pin connects to an internal open-drain, 100V
transistor capable of sinking 1mA. Low impedance indi-
cates power is good. PWRGD is high impedance during
signature and classification probing and in the event of a
thermal overload.
During turn-off, PWRGD is deactivated when the input
voltage drops below 30V. In addition, PWRGD may go
active briefly at turn-on for fast rising input waveforms.
PWRGD is referenced to the V
IN
pin and when active will
be near the V
IN
potential. The PD DC/DC converter will
typically be referenced to V
OUT
and care must be taken to
ensure that the difference in potential of the PWRGD signal
does not cause any detrimental effects. Use of diode clamp
D6, as shown in Figure 10, will alleviate any problems.
Figure 6. LTC4257 Power Good
APPLICATIO S I FOR ATIO
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PWRGD
C1
5µF
MIN
V
IN
6
4
V
OUT
1.125V
R9
100k
5
300k
300k
LTC4257
THERMAL SHUTDOWN
UVLO
4257 F06
TO
PSE
PD
LOAD
SHDN
+
+
+
LTC4257
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Thermal Protection
The LTC4257 includes smart thermal protection in order
to provide full device functionality in a miniature package
while maintaining safe operating temperatures. Several
factors create the possibility for tremendous power
dissi
pation within the LTC4257. IEEE 802.3af mandates
that inrush current be limited to less than 400mA while
standard telecom power can be as high as 57V. At turn on,
before the load capacitor has charged up, the instanta-
neous power dissipated by the LTC4257 can be over 20W.
As the load capacitor charges up, the power dissipation in
the LTC4257 will decrease until it reaches a steady-state
value dependent on the DC load current. The size of the
load capacitor determines how fast the power dissipation
in the LTC4257 subsides. At room temperature, the
LTC4257 can handle load capacitors as large as 800µF
without going into thermal shutdown. With a large load
capacitor like this, the LTC4257 die temperature will
increase by about 50°C during a single turn-on sequence.
If for some reason power were removed from the part and
then quickly reapplied so that the LTC4257 had to charge
up the load capacitor again, the temperature rise would be
excessive if safety precautions were not implemented.
The LTC4257 protects itself from thermal damage by
monitoring the die temperature. If the die temperature
exceeds the overtemperature trip point, the part switches
to a half-power mode where the current limit is set to 50%
of its normal level. This reduces power dissipation and
helps prevent further heating. If the part continues to heat
up and reaches the shutdown temperature, the current is
reduced to zero and very little power is dissipated in the
part until it cools below the overtemperature set point. The
LTC4257 current limit will continue switching between
0%, 50% and 100% current levels (Figure 7) until the load
capacitor is fully charged.
If the PD is designed to operate at a high ambient tempera-
ture and with the maximum allowable supply (57V), there
will be a limit to the size load capacitor that can be charged
up before the LTC4257 reaches the overtemperature trip
point. Hitting the overtemperature trip point intermittently
does not harm the LTC4257, but it will delay completion of
capacitor charging. Capacitors up to 200µF can be charged
without a problem.
During classification, excessive heating of the LTC4257
can occur if the PSE violates the 75ms probing time limit.
To protect the LTC4257, the thermal protection circuitry
will disable classification current if the die temperature
exceeds the overtemperature trip point. When the die
cools down below the trip point, classification current is
re-enabled.
Once the LTC4257 has charged up to the load capacitor
and the PD is powered and running, there will be some
residual heating due to the DC load current of the PD
flowing through the internal MOSFET. In some applica-
tions, the LTC4257 power dissipation may be significant
and if dissipated in the S8 package, excessive package
heating could occur. This problem can be solved with the
use of the DD package which has superior thermal perfor-
mance. The DD package includes an exposed pad that
should be soldered to an isolated heatsink on the printed
circuit board.
Figure 7. Smart Thermal Protection State Diagram
APPLICATIO S I FOR ATIO
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4257 F07
T < 120°C
T < 120°C
T > 120°C
T > 140°C
100%
CURRENT
UVLO
TURN ON
50%
CURRENT
0%
CURRENT
LTC4257
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EXTERNAL INTERFACE AND COMPONENT SELECTION
Transformer
Nodes on an Ethernet network commonly interface to the
outside world via an isolation transformer (Figure 8). For
powered devices, the isolation transformer must include
a center tap on the media (cable) side. Proper termination
is required around the transformer to provide correct
impedance matching and to avoid radiated and conducted
emissions. Transformer vendors such as Pulse, Bel Fuse,
Tyco and others (Table 3) can provide assistance with
selection of an appropriate isolation transformer and
proper termination methods. These vendors have trans-
formers specifically designed for use in PD applications.
Table 3. Power over Ethernet Transformer Vendors
VENDOR CONTACT INFORMATION
Pulse Engineering 12220 World Trade Drive
San Diego, CA 92128
Tel: 858-674-8100
FAX: 858-674-8262
http://www.pulseeng.com/
Bel Fuse Inc. 206 Van Vorst Street
Jersey City, NJ 07302
Tel: 201-432-0463
FAX: 201-432-9542
http://www.belfuse.com/
Tyco Electronics 308 Constitution Drive
Menlo Park, CA 94025-1164
Tel: 800-227-7040
FAX: 650-361-2508
http://www.circuitprotection.com/
Diode Bridges
IEEE 802.3af allows power wiring in either of two configu-
rations on the TX/RX wires, plus power can be applied to
the PD via the spare wire pair in the RJ45 connector. The
PD is required to accept power in either polarity on both
the main and spare inputs, therefore it is common to install
diode bridges on both inputs in order to accommodate the
different wiring configurations. Figure 8 demonstrates an
implementation of these diode bridges. The specification
also mandates that the leakage back through the unused
bridge be less than 28µA when the PD is powered with
57V.
The IEEE standard includes an AC impedance requirement
in order to implement the AC disconnect function. Capaci-
tor C14 in Figure 8 is used to meet this AC impedance
requirement. A 0.1µF capacitor is recommended for this
application.
The LTC4257 has several different modes of operation
based on the voltage present between the V
IN
and GND
pins. The forward voltage drop of the input diodes in a PD
design subtracts from the input voltage and will affect the
transition point between modes. When using the LTC4257,
it is necessary to pay close attention to this forward
voltage drop. Selection of oversized diodes will help keep
the PD thresholds from exceeding IEEE specifications.
The input diode bridge of a PD can consume 4% of the
avialable power in some applications. It may be desirable
to use Scottky diodes in order to reduce this power loss.
APPLICATIO S I FOR ATIO
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Figure 8. PD Front End with Isolation Transformer, Diode Bridges and Capacitor
16
14
15
1
3
2
RX
6
RX
+
3
TX
2
TX
+
RJ45
T1
PULSE H2019
4257 F08
1
7
8
5
4
11
9
10
6
8
7
D3
SMAJ58A
TVS
BR1
DF01SA
BR2
DF01SA
TO PHY
GND
8
54
LTC4257
C1
V
IN
V
OUT
V
OUT
SPARE
SPARE
+
C14
0.1µF
100V

LTC4257IDD#TRPBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Power Switch ICs - POE / LAN IEEE 802.3af PD Pwr over E Int Cntr
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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