LTC4257
6
4257fb
The LTC4257 is intended for use as the front end of a
Powered Device (PD) designed to IEEE 802.3af draft
standard. The LTC4257 includes a trimmed 25k signature
resistor, classification current source, and an inrush cur-
rent limit circuit. With these functions integrated into the
LTC4257, the signature and power interface for a PD that
meets all the requirements of IEEE 802.3af can be built
with a minimum of external components.
Using an LTC4257 for the power and signature interface
functions of a PD provides several advantages. The
LTC4257 current limit circuit includes an onboard, 100V,
400mA power MOSFET with low leakage. This onboard
low leakage MOSFET avoids the possibility of corrupting
the 25k signature resistor while also saving board space
and cost. In addition, the IEEE 802.3af inrush current limit
requirement causes large transient power dissipation in
the PD; the LTC4257 manages this turn-on sequence
through the use of smart thermal protection circuitry. The
LTC4257 is designed to allow multiple turn-on sequences
without overheating the miniature 8-lead package. In the
event of excessive power cycling, the LTC4257 provides
thermally activated current-limit reduction to keep the
onboard power MOSFET within its safe operating area.
Operation
The LTC4257 has several modes of operation depending
on the applied input voltage as shown in Figure 1 and
summarized in Table 1. These various modes satisfy the
requirements defined in the IEEE 802.3af specification.
The input voltage is applied to the V
IN
pin and is with
reference to the GND pin. This input voltage is always
negative. To avoid confusion, voltages in this data sheet
are always referred to in terms of absolute magnitude.
Terms such as
maximum negative voltage
refer to the
largest negative voltage and a
rising negative voltage
refers to a voltage that is becoming more negative. Refer-
ences to electrical parameters in this applications section
use the nominal value. Refer to the Electrical Characteris-
tics section for the range of values a particular parameter
will have.
DETECTION V1
CLASSIFICATION
UVLO
TURN-ON
UVLO
OFF
POWER
BAD
UVLO
OFF
UVLO
ON
UVLO
TURN-OFF
τ = R
LOAD
C1
PWRGD TRACKS
V
IN
DETECTION V2
–10
TIME
–20
–30
V
IN
(V)
–40
–50
–10
TIME
–20
–30
V
OUT
(V)
–40
–50
–10
TIME
–20
–30
PWRGD (V)
–40
–50
I
CLASS
PD CURRENT
I
LIMIT
dV
dt
I
LIMIT
C1
=
POWER
BAD
POWER
GOOD
DETECTION I
1
CLASSIFICATION
I
CLASS
DETECTION I
2
LOAD CURRENT, I
LOAD
CURRENT
LIMIT, I
LIMIT
4257 F01
I
CLASS
DEPENDENT ON R
CLASS
SELECTION
I
LIMIT
= 350mA (NOMINAL)
I
1
=
V1 – 2 DIODE DROPS
25kΩ
I
LOAD
=
V
IN
R
LOAD
I
2
=
V2 – 2 DIODE DROPS
25kΩ
GND
2
PSE
I
IN
8
6
5
R9 R
LOAD
R
CLASS
V
OUT
C1
GND
4
R
CLASS
PWRGD
LTC4257
V
OUT
V
IN
V
IN
Figure 1. Output Voltage, PWRGD and PD Current
as a Function of Input Voltage
APPLICATIO S I FOR ATIO
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