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87321AMILF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
÷1, ÷2 Differential-TO-LVPECL
Clock Generator
87321I
Data Sheet
©2016 Integrated Device Technology, Inc Revision A January 25, 20161
GENERAL DESCRIPTION
The 87321I is a high performance ÷1, ÷2 Differential-to-LVPECL
Clock Generator and a member of the amily of High Performance
Clock Solutions from IDT. The CLK, nCLK pair can accept most stan-
dard differential input levels. The 87321I is characterized to operate
from a 3.3V or 2.5V power supply. Guaranteed part-to-part skew
characteristics make the 87321I ideal for those clock distribution
applications demanding well defi ned performance and repeatability.
FEATURES
• One differential LVPECL output
• One CLK, nCLK input pair
• CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
• Maximum clock input frequency: 700MHz
• Translates any single ended input signal (LVCMOS, LVTTL,
GTL) to LVPECL levels with resistor bias on nCLK input
• Part-to-part skew: 600ps (maximum)
• Propagation delay: 1.8ns (maximum)
• Additive phase Jitter, RMS: 0.18ps
• Full 3.3V or 2.5V operating supply
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
BLOCK DIAGRAM PIN ASSIGNMENT
87321I
8-Lead SOIC
3.90mm x 4.90mm x 1.37mm package body
M Package
Top View
CLK
nCLK
MR
F_SEL
1
2
3
4
Vcc
Q
nQ
V
EE
8
7
6
5
0
1
÷1
÷2
R
CLK
nCLK
MR
F_SEL
Q
nQ
Pulldown
Pulldown
Pulldown
Pullup
87321I Data Sheet
©2016 Integrated Device Technology, Inc Revision A January 25, 20162
TABLE 1. PIN DESCRIPTIONS
TABLE 2. PIN CHARACTERISTICS
TABLE 3. FUNCTION TABLE
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 4 pF
R
PULLUP
Input Pullup Resistor 51
kΩ
R
PULLDOWN
Input Pulldown Resistor 51
kΩ
MR F_SEL Divide Value
1 X Reset: Q output low, nQ output high
00 ÷1
01 ÷2
Number Name Type Description
1 CLK Input Pulldown Non-inverting differential clock input.
2 nCLK Input Pullup Inverting differential clock input.
3 MR Input Pulldown
Active High Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs (Q) to go low and the inverted outputs
(nQ) to go high. When logic LOW, the internal dividers and the outputs
are enabled. LVCMOS / LVTTL interface levels. See Table 3.
4 F_SEL Input Pulldown
Selects divider value for Q, nQ outputs as described in Table 3.
LVCMOS / LVTTL interface levels.
5V
EE
Power Negative supply pin.
6, 7 nQ, Q Output Differential output pair. LVPECL interface levels.
8V
CC
Power Positive supply pin.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
87321I Data Sheet
©2016 Integrated Device Technology, Inc Revision A January 25, 20163
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
CC
4.6V
Inputs, V
I
-0.5V to V
CC
+ 0.5 V
Outputs, I
O
Continuous Current 50mA
Surge Current 100mA
Package Thermal Impedance, θ
JA
95°C/W (0 lfpm)
Storage Temperature, T
STG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifi cations only. Functional
operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
CC
Positive Supply Voltage 3.135 3.3 3.465 V
I
EE
Power Supply Current 18 mA
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, V
CC
= 3.3V±5%, V
EE
= 0V, TA = -40°C TO 85°C
TABLE 4D. DIFFERENTIAL DC CHARACTERISTICS, V
CC
= 3.3V±5% OR 2.5V±5%, V
EE
= 0V, TA = -40°C TO 85°C
TABLE 4C. LVCMOS/LVTTL DC CHARACTERISTICS, V
CC
= 3.3V±5% OR 2.5V±5%, V
EE
= 0V, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
I
IH
Input High Current
CLK V
CC
= V
IN
= 3.465V or 2.625V 150 µA
nCLK V
CC
= V
IN
= 3.465V or 2.625V 5 µA
I
IL
Input Low Current
CLK V
CC
= 3.465V, or 2.625V V
IN
= 0V -5 µA
nCLK V
CC
= 3.465V or 2.625V, V
IN
= 0V -150 µA
V
PP
Peak-to-Peak Input Voltage;
NOTE 1
0.15 1.3 V
V
CMR
Common Mode Input Voltage;
NOTE 1, 2
V
EE
+ 0.5 V
CC
- 0.85 V
NOTE 1: V
IL
should not be less than -0.3V.
NOTE 2: Common mode voltage is defi ned as V
IH
.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
IH
Input High Voltage
V
CC
= 3.3V 2 V
CC
+ 0.3 V
V
CC
= 2.5V 1.7 V
CC
+ 0.3 V
V
IL
Input Low Voltage
V
CC
= 3.3V -0.3 0.8 V
V
CC
= 2.5V -0.3 0.7 V
V
HYS
Input Hysteresis MR, F_SEL 100 mV
I
IH
Input High Current MR, F_SEL V
CC
= V
IN
= 3.465V or 2.625V 150 µA
I
IL
Input Low Current MR, F_SEL V
CC
= 3.465V, or 2.625V V
IN
= 0V -5 µA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
CC
Positive Supply Voltage 2.375 2.5 2.625 V
I
EE
Power Supply Current 16 mA
TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, V
CC
= 2.5V±5%, V
EE
= 0V, TA = -40°C TO 85°C
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

87321AMILF

Mfr. #:
Buy 87321AMILF
Manufacturer:
IDT
Description:
Clock Generators & Support Products 1 LVPECL OUT DIVIDER
Lifecycle:
New from this manufacturer.
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