87321I Data Sheet
©2016 Integrated Device Technology, Inc Revision A January 25, 201610
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are recom-
mended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that generate
ECL/LVPECL compatible outputs. Therefore, terminating resistors
(DC current path to ground) or current sources must be used for
functionality. These outputs are designed to drive 50Ω transmission
lines. Matched impedance techniques should be used to maximize
operating frequency and minimize signal distortion. Figures 3A
and 3B show two different layouts which are recommended only
as guidelines. Other suitable clock layouts may exist and it would
be recommended that the board designers simulate to guarantee
compatibility across all printed circuit and clock component process
variations.
TERMINATION FOR 3.3V LVPECL OUTPUTS
FIGURE 3B. LVPECL OUTPUT TERMINATIONFIGURE 3A. LVPECL OUTPUT TERMINATION
INPUTS:
LVCMOS CONTROL PINS
All control pins have internal pulldowns; additional resistance is not
required but can be added for additional protection. A 1kΩ resistor
can be used.
RECOMMENDATIONS FOR UNUSED INPUT PINS
87321I Data Sheet
©2016 Integrated Device Technology, Inc Revision A January 25, 201611
TERMINATION FOR 2.5V LVPECL OUTPUTS
Figure 4A and Figure 4B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminating
50Ω to V
CC
- 2V. For V
CC
= 2.5V, the V
CC
- 2V is very close to ground
level. The R3 in Figure 4B can be eliminated and the termination
is shown in Figure 4C.
FIGURE 4C. 2.5V LVPECL TERMINATION EXAMPLE
R2
50
Zo = 50 Ohm
VCCO=2.5V
R1
50
Zo = 50 Ohm
+
-
2.5V
2,5V LVPECL
Driver
FIGURE 4B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 4A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
R2
62.5
2.5V
2,5V LVPECL
Driver
R3
250
Zo = 50 Ohm
Zo = 50 Ohm
R4
62.5
2.5V
+
-
R1
250
VCCO=2.5V
87321I Data Sheet
©2016 Integrated Device Technology, Inc Revision A January 25, 201612
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the 87321I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the 87321I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipation into the load.
Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.465V * 18mA = 62.37mW
Power (outputs)
MAX
= 30mW/Loaded Output pair
Total Power
_MAX
(3.465V, with outputs switching) = 62.37mW + 30mW = 92.37mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θ
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ
JA
must be used. Assuming no air fl ow
and a multi-layer board, the appropriate value is 95.0°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with output switching is:
85°C + 0.092W *95°C/W = 93.7°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air fl ow,
and the type of board (multi-layer).
TABLE 6. THERMAL RESISTANCE θ
JA
FOR 8-PIN SOIC, FORCED CONVECTION
θ
JA
by Velocity (Linear Feet per Minute)
0 200 500
Multi-Layer PCB, JEDEC Standard Test Boards 95.0°C/W 88.4°C/W 83.7°C/W

87321AMILF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Generators & Support Products 1 LVPECL OUT DIVIDER
Lifecycle:
New from this manufacturer.
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