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87321AMILF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
87321I Data Sheet
©2016 Integrated Device Technology, Inc Revision A January 25, 20164
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
CLK
Clock Input Frequency 700 MHz
t
PD
Propagation Delay;
NOTE 1
CLK to
Q (Dif)
1.2 1.8 ns
tjit
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter
Section
155.52MHz, Integration Range:
(12kHz - 20MHz)
0.18 ps
tsk(pp) Part-to-Part Skew; NOTE 2, 3 600 ps
t
R
/ t
F
Output Rise/Fall Time 20% to 80% 100 600 ps
odc Output Duty Cycle; NOTE 4 48 53 %
NOTE: Electrical parameters are guaranteed over the specifi ed ambient operating temperature range, which is established
when the device is mounted in a test socket with maintained transverse airfl ow greater than 500 lfpm. The device will meet
specifi cations after thermal equilibrium has been reached under these conditions.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defi ned as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 3: This parameter is defi ned in accordance with JEDEC Standard 65.
NOTE 4: Input duty cycle must be 50%.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
OH
Output High Voltage; NOTE 1 V
CC
- 1.4 V
CC
- 0.9 V
V
OL
Output Low Voltage; NOTE 1 V
CC
- 2.0 V
CC
- 1.7 V
V
SWING
Peak-to-Peak Output Voltage Swing 0.65 1.0 V
NOTE 1: Outputs terminated with 50Ω to V
CC
- 2V.
TABLE 5A. AC CHARACTERISTICS, V
CC
= 3.3V±5%, V
EE
= 0V, TA = -40°C TO 85°C
TABLE 4E. LVPECL DC CHARACTERISTICS, V
CC
= 3.3V±5%, V
EE
= 0V, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
OH
Output High Voltage; NOTE 1 V
CC
- 1.4 V
CC
- 0.9 V
V
OL
Output Low Voltage; NOTE 1 V
CC
- 2.0 V
CC
- 1.5 V
V
SWING
Peak-to-Peak Output Voltage Swing 0.4 1.0 V
NOTE 1: Outputs terminated with 50Ω to V
CC
- 2V.
TABLE 4E. LVPECL DC CHARACTERISTICS, V
CC
= 2.5V±5%, V
EE
= 0V, TA = -40°C TO 85°C
87321I Data Sheet
©2016 Integrated Device Technology, Inc Revision A January 25, 20165
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
CLK
Clock Input Frequency 700 MHz
t
PD
Propagation Delay;
NOTE 1
CLK to
Q (Dif)
1.2 1.8 ns
tjit
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter
Section
155.52MHz, Integration Range:
(12kHz - 20MHz)
0.18 ps
tsk(pp) Part-to-Part Skew; NOTE 2, 3 600 ps
t
R
/ t
F
Output Rise/Fall Time 20% to 80% 100 600 ps
odc Output Duty Cycle; NOTE 4 45 55 %
NOTE: Electrical parameters are guaranteed over the specifi ed ambient operating temperature range, which is established
when the device is mounted in a test socket with maintained transverse airfl ow greater than 500 lfpm. The device will meet
specifi cations after thermal equilibrium has been reached under these conditions.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defi ned as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 3: This parameter is defi ned in accordance with JEDEC Standard 65.
NOTE 4: Input duy cycle must be 50%.
TABLE 5B. AC CHARACTERISTICS, V
CC
= 2.5V±5%, V
EE
= 0V, TA = -40°C TO 85°C
87321I Data Sheet
©2016 Integrated Device Technology, Inc Revision A January 25, 20166
ADDITIVE PHASE JITTER
The spectral purity in a band at a specifi c offset from the fundamental
compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot
and is most often the specifi ed plot in many applications. Phase
noise is defi ned as the ratio of the noise power present in a 1Hz
band at a specifi ed offset from the fundamental frequency to the
power value of the fundamental. This ratio is expressed in decibels
As with most timing specifi cations, phase noise measurements has
issues relating to the limitations of the equipment. Often the noise
fl oor of the equipment is higher than the noise fl oor of the device.
(dBm) or a ratio of the power in the 1Hz band to the power in the
fundamental. When the required offset is specifi ed, the phase noise
is called a dBc value, which simply means dBm at a specifi ed offset
from the fundamental. By investigating jitter in the frequency domain,
we get a better understanding of its effects on the desired application
over the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
This is illustrated above. The device meets the noise fl oor of what
is shown, but can actually be lower. The phase noise is dependent
on the input source and measurement equipment.
OFFSET FROM CARRIER FREQUENCY (HZ)
SSB PHASE NOISE dBc/HZ
Additive Phase Jitter @
155.52MHz (12kHz to 20MHz) = 0.18ps typical
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

87321AMILF

Mfr. #:
Buy 87321AMILF
Manufacturer:
IDT
Description:
Clock Generators & Support Products 1 LVPECL OUT DIVIDER
Lifecycle:
New from this manufacturer.
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