ADL5315ACPZ-R7 Datasheet ADL5315ACPZ-R7 | P10-P12

ADL5315

Rev. 0 | Page 9 of 20

THEORY OF OPERATION

The ADL5315 addresses the need for precision high-side

monitoring of photodiode current in fiber optic systems and is

useful in many nonoptical applications as well. It is optimized

for use with ADI’s family of translinear logarithmic amplifiers,

which take advantage of the wide input current range of the

ADL5315. This arrangement allows the anode of the photo-

diode to connect directly to a transimpedance amplifier for the

extraction of the data stream without the need for a separate

optical power monitoring tap.

Figure 19 shows the basic

connections for the ADL5315.

ADL5315

COMM

VSET NC

VOLTAGE

SUPPLY

MIRROR

CURRENT

OUTPUT

INPT

2 7

SREF

VPOS

RLIM

IOUT

0.01μF0.1μF

2.2nF

LIM

390pF

4kΩ

05694-023

Figure 19. Basic Connections

At the heart of the ADL5315 is a precision 1:1 current

mirror with a voltage following characteristic that provides an

adjustable bias voltage at the mirror input. This architecture

uses a JFET input amplifier to drive the bipolar mirror and

maintain stable V

INPT

voltage, while offering very low leakage

current at the INPT pin. The current sourced by the low

impedance INPT pin is mirrored and sourced by the high

impedance IOUT pin.

BIAS CONTROL INTERFACE

The voltage at the INPT pin, V

INPT

, is forced to be equal to the

voltage applied to VSET by the mirror-biasing loop. The V

SET

voltage range extends down to ground, allowing the ADL5315

to be used as a voltage-to-current converter with a single resistor

from INPT to ground. This capability allows dark current to be

minimized in PIN photodiode systems by maintaining a small

voltage bias. The VSET control also allows V

INPT

to be set

approximately equal to the load voltage at IOUT. Balancing

the mirror voltages in this way provides inherently superior

linearity over the widest current range independent of the

supply voltage. Only leakage currents from the JFET op amp

and ESD devices remain as significant sources of nonlinearity

at very low currents. The voltage at VSET can also be used to

shield the highly sensitive INPT pin and its board trace from

leakage currents, because the two pins operate at approximately

the same potential. Care must be taken to provide a low noise

SET

signal, since voltage noise at VSET also appears at INPT

and is transformed by the input compensation network into

current noise.

The ADL5315 provides a setpoint reference pin, SREF,

which can be connected to VSET for standard 2-port

mirror operation. V

SREF

is maintained 1.0 V below V

POS

over

temperature and is independent of input current. When using

SREF to set the input voltage, a capacitor should be placed

between SREF and ground to filter noise from SREF as well

as improve power supply rejection over frequency. A value of

2.2 nF, for example, combined with the 20 kΩ output resistance

at SREF, creates a pole at approximately 3 kHz.

The voltage at the SREF pin can be lowered to a desired fixed

value with the use of a single external resistor from SREF to

ground. Mismatch between on-chip and external resistors

limits the accuracy of the resultant voltage. In addition, internal

clamping to protect the precision bias limits the range.

Figure 20

shows an equivalent circuit model of the SREF biasing. The

Schottky diode clamp protects the 50 µA current source when

SREF is pulled to ground. When V

SREF

is 1.2 V or higher, the

50 µA current flows to the SREF pin. The current is shunted

away and does not appear at the SREF pin for V

SREF

< 0.6 V.

The transition region is between 0.6 V and 1.2 V with a large

uncertainty in the pull-down current. It is recommended that a

2-resistor divider from VPOS (with no connection to SREF) or

another external bias be used to bias VREF in this transition

region.

Equations for the SREF voltage with an external pull-down R

EXT

follow:

()

V 1V 1

k2

2.,0.

≥−

SREFPOS

EXT

SREF

k2

6.0,

≤

SREFPOS

EXT

SREF

where the 20 kΩ is the process-dependent internal resistor.

VSET

POS

SET

ADL5315

05964-029

SREF

50μA

EXT

0.9V

20kΩ

Figure 20. Model of SREF Bias Source with External Pull-Down

ADL5315

Rev. 0 | Page 10 of 20

The VSET control is intended primarily to provide a dc bias

voltage for the mirror input, but it is also well behaved in the

presence of the V

SET

transients. The rise time of V

INPT

is largely

independent of input current because the mirror is capable of

sourcing large currents to pull up the INPT pin. The fall time,

however, is inversely proportional to I

INPT

because only I

INPT

available to discharge the input compensation capacitor and

other parasitics (see

Figure 11). The mirror output current can

vary significantly from zero to several milliamps until V

INPT

fully settled.

NOISE PERFORMANCE

The noise performance for the ADL5315, defined as the rms

noise current as a fraction of the output dc current, generally

improves with increasing signal current. This partially results

from the relationship between the quiescent collector current

and the shot noise in the bipolar transistors. At lower signal

current levels, the noise contribution from the JFET amplifier

and other voltage noise sources appearing at INPT contribute

significantly to the current noise. Filtering noise at VSET,

whether provided by SREF or generated externally, as well as

selecting optimal external compensation components on INPT,

minimizes the amount of current noise at IOUT generated by

the voltage noise at INPT.

MIRROR RESPONSE TIME

The response time of I

OUT

to changes in I

INPT

is fundamentally a

function of input current, with small-signal bandwidth increasing

roughly in proportion to I

INPT

(see Figure 10). The value of the

external compensating capacitor on INPT strongly affects the

OUT

response time (as well as the V

SET

to V

INPT

fall time, as noted

in the

Bias Control Interface section), although the value must

be chosen to maintain stability and prevent noise peaking.

INPUT CURRENT LIMITING

The ADL5315 provides a resistor-programmable input current

limit with a fixed maximum of 16 mA for the RLIM pin tied to

VPOS. The fixed maximum provides input short-circuit protection

to ground. The current limit is defined as the current that forces

INPT

to 0 V (when using a current source on the INPT pin).

Resistor R

LIM

between the VPOS and RLIM pins controls the

current limit according to

k3

V 48

LIM

over an R

LIM

range of 0 to 45 kΩ, corresponding to 16 mA down

to 1 mA. Larger values of R

LIM

can be used for currents below

1 mA (down to approximately 250 µA) with some degradation

in accuracy. See

Figure 14 for more performance detail.

ADL5315

Rev. 0 | Page 11 of 20

APPLICATIONS

The ADL5315 is primarily designed for wide dynamic range

applications, simplifying power monitoring designs where

access is only permitted to the cathode of a PIN photodiode or

receiver module.

Figure 22 shows a typical application where

the ADL5315 is used to provide an accurate bias to a PIN diode

while simultaneously mirroring the diode current to be

measured by a translinear logarithmic amplifier.

In this application, the ADL5315 sets the bias voltage on the

PIN diode. This voltage is delivered at the INPT pin and is

controlled by the voltage at the VSET pin. VSET is driven by

the on-board reference V

SREF

, which is equal to V

POS

− 1 V.

The input current, I

INPT

, is precisely mirrored at a ratio of 1:1 to

the IOUT pin. This interface is optimized for use with any of

ADI’s translinear logarithmic amplifiers (for example, the

AD8304 or AD8305) to offer a precise, wide dynamic range

measurement of the optical power incident upon the PIN.

If a linear voltage output is preferred at IOUT, a single external

resistor to ground is all that is necessary to perform the

conversion.

AVERAGE POWER MONITORING

In applications where a modulated signal is incident upon the

photodiode, the average power of the signal can be measured.

Figure 21 shows the connections necessary for using the

ADL5315 in such a measurement system.

The value of the capacitor to ground should be selected to

eliminate errors due to modulation of the ADL5315 input

current.

VOLTAGE

REFERENCE

CURRENT

LIMITING

COMM

VSET NC

INPT

DATA PATH

LINEAR

VOLTAGE

OUTPUT

CURRENT

MIRROR

1:1

ADL5315

2 7

SREF

VPOS

20kΩ

RLIM

SET

POS

IOUT

TIA

05694-010

Figure 21. Average Power Monitoring Using the ADL5315

VOLTAGE

REFERENCE

CURRENT

LIMITING

COMM

VSET NC

INPT

DATA PATH

OPTICAL

POWER

TRANSLINEAR LOG AMP

AD8304, AD8305, ETC.

THIS CONNECTION IS NOT NECESSARY,

BUT REDUCES ERRORS DUE TO LEAKAGE

CURRENTS AT LOW SIGNAL LEVELS.

CURRENT

MIRROR

1:1

ADL5315

2 7

SREF

VPOS

POS

20kΩ

RLIM

LIM

= 48V

LIM

LIM =

1mA – 16mA

– 3kΩ

IOUT

VSUM

INPT

TIA

SREF

= V

POS

– 1V

SET

= V

INPT

NODE VOLTAGES

05694-009

Figure 22. Typical Application Using the ADL5315

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21

ADL5315ACPZ-R7

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Manufacturer:

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Description:

Current & Power Monitors & Regulators 5V Current Mirror

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ADL5315ACPZ-R7