IS61LPS102436A-166TQLI

Integrated Silicon Solution, Inc. 1

Rev. C

05/27/2010

Copyright © 2010 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no

liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on

any published information and before placing orders for products.

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause

failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written

assurance to its satisfaction, that:

• Internalself-timedwritecycle

• IndividualByteWriteControlandGlobalWrite

• Clockcontrolled,registeredaddress,dataand

control

• BurstsequencecontrolusingMODEinput

• Threechipenableoptionforsimpledepthex-

pansion and address pipelining

• Commondatainputsanddataoutputs

• AutoPower-downduringdeselect

• Singlecycledeselect

• JEDEC100-PinTQFPand165-ballPBGA

packages

• Lead-freeavailable

DESCRIPTION

The ISSI IS61LPS/VPS102436A and IS61LPS/VPS

204818Aarehigh-speed,low-powersynchronousstatic

RAMs

designed to provide burstable,

high-performance

memory for communication and networking applications.

TheIS61LPS/VPS102436Aisorganizedas1,048,476

wordsby36bits.TheIS61LPS/VPS204818A is organized

Writecyclesareinternallyself-timedandareinitiatedby

therisingedgeoftheclockinput.Writecyclescanbe

one to four bytes wide as controlled by the write control

inputs.

Separate byte enables allow individual bytes to be written.

Thebytewriteoperationisperformedbyusingthebyte

write enable (BWE) input combined with one or more

individual byte write signals (BWx). Inaddition,Global

Write(GW) is available for writing all bytes at one time,

regardless of the byte write controls.

der,LinearburstisachievedwhenthispinistiedLOW.

InterleaveburstisachievedwhenthispinistiedHIGH

or left floating.

1Mb x 36, 2Mb x 18

36Mb SYNCHRONOUS PIPELINED,

SINGLE CYCLE DESELECT STATIC RAM

FAST ACCESS TIME

Symbol Parameter 200 166 Units

tk q ClockAccessTime 3.1 3.5 ns

Integrated Silicon Solution, Inc.3

Rev. C

05/27/2010