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IS61LPS102436A-166TQLI

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
4 Integrated Silicon Solution, Inc.
Rev. C
05/27/2010
IS61VPS102436A, IS61LPS102436A, IS61VPS204818A, IS61LPS204818A
PIN DESCRIPTIONS
165 PBGA PACKAGE PIN CONFIGURATION
1M x 36 (TOP VIEW)
Note: * A0 and A1arethetwoleastsignicantbits(LSB)oftheaddresseldandsettheinternalburstcounterifburstisdesired.
1 2 3 4 5 6 7 8 9 10 11
A
NC A
CE BWc BWb CE2 BWE ADSC ADV
A NC
B
NC A CE2
BWd BWa
CLK
GW OE ADSP
A NC
C
DQPc NC V
d d q Vss Vss Vss Vss Vss Vd d q Nc
DQPb
D
DQc DQc V
d d q Vd d Vss Vss Vss Vd d Vd d q
DQb DQb
E
DQc DQc V
d d q Vd d Vss Vss Vss Vd d Vd d q
DQb DQb
F
DQc DQc V
d d q Vd d Vss Vss Vss Vd d Vd d q
DQb DQb
G
DQc DQc V
d d q Vd d Vss Vss Vss Vd d Vd d q
DQb DQb
H
NC NC NC V
d d Vss Vss Vss Vd d Nc Nc ZZ
J
DQd DQd V
d d q Vd d Vss Vss Vss Vd d Vd d q dqa dqa
K
DQd DQd V
d d q Vd d Vss Vss Vss Vd d Vd d q dqa dqa
L
DQd DQd V
d d q Vd d Vss Vss Vss Vd d Vd d q dqa dqa
M
DQd DQd V
d d q Vd d Vss Vss Vss Vd d Vd d q dqa dqa
N
DQPd NC V
d d q Vss NC A NC Vss Vd d q NC DQPa
P
NC NC A A NC A
1* NC A A A A
R
MODE A A A NC A
0* NC A A A A
Symbol Pin Name
A Address Inputs
A0, A1 SynchronousBurstAddressInputs
ADV SynchronousBurstAddress
Advance
ADSP Address Status Processor
ADSC Address Status Controller
GW GlobalWriteEnable
CLK Synchronous Clock
CE, CE2, CE2 Synchronous Chip Select
BWx(x=a,b,c,d) SynchronousByteWrite
Controls
Symbol Pin Name
BWE ByteWriteEnable
OE OutputEnable
ZZ PowerSleepMode
MODE BurstSequenceSelection
NC No Connect
DQx DataInputs/Outputs
DQPx DataInputs/Outputs
Vd d 3.3V/2.5VPowerSupply
Vd d q IsolatedOutputPowerSupply
3.3V/2.5V
Vss Ground
Integrated Silicon Solution, Inc. 5
Rev. C
05/27/2010
IS61VPS102436A, IS61LPS102436A, IS61VPS204818A, IS61LPS204818A
Note: * A0 and A1arethetwoleastsignicantbits(LSB)oftheaddresseldandsettheinternalburstcounterifburstisdesired.
165 PBGA PACKAGE PIN CONFIGURATION
2M x 18 (TOP VIEW)
PIN DESCRIPTIONS
Symbol Pin Name
A Address Inputs
A0, A1 SynchronousBurstAddressInputs
ADV SynchronousBurstAddress
Advance
ADSP Address Status Processor
ADSC Address Status Controller
GW GlobalWriteEnable
CLK Synchronous Clock
CE, CE2, CE2 Synchronous Chip Select
BWx(x=a,b) SynchronousByteWrite
Controls
Symbol Pin Name
BWE ByteWriteEnable
OE OutputEnable
ZZ PowerSleepMode
MODE BurstSequenceSelection
NC No Connect
DQx DataInputs/Outputs
DQPx DataInputs/Outputs
Vd d 3.3V/2.5VPowerSupply
Vd d q IsolatedOutputPowerSupply
3.3V/2.5V
Vss Ground
1 2 3 4 5 6 7 8 9 10 11
A
NC A
CE BWb
NC
CE2 BWE ADSC ADV
A A
B
NC A CE2 NC
BWa
CLK
GW OE ADSP
A NC
C
NC NC V
d d q Vss Vss Vss Vss Vss Vd d q Nc
DQPa
D
NC DQb V
d d q Vd d Vss Vss Vss Vd d Vd d q
NC DQa
E
NC DQb V
d d q Vd d Vss Vss Vss Vd d Vd d q
NC DQa
F
NC DQb V
d d q Vd d Vss Vss Vss Vd d Vd d q
NC DQa
G
NC DQb V
d d q Vd d Vss Vss Vss Vd d Vd d q
NC DQa
H
NC NC NC V
d d Vss Vss Vss Vd d Nc Nc ZZ
J
DQb NC V
d d q Vd d Vss Vss Vss Vd d Vd d q dqa Nc
K
DQb NC V
d d q Vd d Vss Vss Vss Vd d Vd d q dqa Nc
L
DQb NC V
d d q Vd d Vss Vss Vss Vd d Vd d q dqa Nc
M
DQb NC V
d d q Vd d Vss Vss Vss Vd d Vd d q dqa Nc
N
DQPb NC V
d d q Vss NC A NC Vss Vd d q NC NC
P
NC NC A A NC A
1* NC A A A A
R
MODE A A A NC A
0* NC A A A A
6 Integrated Silicon Solution, Inc.
Rev. C
05/27/2010
IS61VPS102436A, IS61LPS102436A, IS61VPS204818A, IS61LPS204818A
DQPb
DQb
DQb
VDDQ
VSS
DQb
DQb
DQb
DQb
VSS
VDDQ
DQb
DQb
VSS
NC
VDD
ZZ
DQa
DQa
VDDQ
VSS
DQa
DQa
DQa
DQa
VSS
VDDQ
DQa
DQa
DQPa
A
A
CE
CE2
BWd
BWc
BWb
BWa
CE2
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
DQPc
DQc
DQc
VDDQ
VSS
DQc
DQc
DQc
DQc
VSS
VDDQ
DQc
DQc
NC
VDD
NC
VSS
DQd
DQd
VDDQ
VSS
DQd
DQd
DQd
DQd
VSS
VDDQ
DQd
DQd
DQPd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
MODE
A
A
A
A
A1
A0
NC
A
VSS
VDD
A
A
A
A
A
A
A
A
A
46 47 48 49 50
PIN DESCRIPTIONS
A0, A1 SynchronousAddressInputs.These
pinsmusttiedtothetwoLSBsofthe
address bus.
A Synchronous Address Inputs
ADSC
Synchronous Controller Address Status
ADSP
Synchronous Processor Address Status
ADV
SynchronousBurstAddressAdvance
BWa-BWd SynchronousByteWriteEnable
BWE SynchronousByteWriteEnable
CE, CE2, CE2 SynchronousChipEnable
CLK Synchronous Clock
DQa-DQd SynchronousDataInput/Output
DQPa-DQPd ParityDataInput/Output
GW SynchronousGlobalWriteEnable
MODE BurstSequenceModeSelection
OE OutputEnable
Vd d 3.3V/2.5VPowerSupply
Vd d q IsolatedOutputBufferSupply:
3.3V/2.5V
Vss Ground
ZZ SnoozeEnable
PIN CONFIGURATION
1M x 36
100-PIN TQFP
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

IS61LPS102436A-166TQLI

Mfr. #:
Buy IS61LPS102436A-166TQLI
Manufacturer:
ISSI
Description:
SRAM 36M (1Mx36) 166MHz Sync SRAM 3.3v
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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