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P5020NXE1TNB

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Features
P5020 QorIQ Communications Processor Product Brief, Rev. 1
Freescale Semiconductor 25
4-Kbyte granularity); other CPU MMUs are not configured for access to the other CPU’s private memory
range. When two CPUs need to share resources, their MMUs are both configured so that they have access
to the shared address range.
This level of hardware support for partitioning is common today, however, it is not sufficient for many core
systems running diverse software. When the functions of multiple discrete CPUs are consolidated onto a
single, multicore SoC, achieving strong partitioning should not require the developer to map functions onto
cores that are the exclusive owners of specific platform resources. The alternative, a fully open system with
no private resources, is also unacceptable. For this reason, the core MMU also includes embedded
Hypervisor extensions.
Each core MMU supports three levels of instructions:
• User
• Supervisor (OS)
• Hypervisor: An embedded Hypervisor micro-kernel (provided by Freescale as source code) runs
unobtrusively beneath the various OSes running on the CPUs, consuming CPU cycles only when
an access attempt is made to an embedded Hypervisor-managed shared resource.The embedded
Hypervisor determines whether the access should be allowed, and if so, proxies the access on
behalf of the original requestor. If malicious or poorly tested software on any core attempts to
overwrite important P5020 configuration registers (including CPU MMUs), the embedded
Hypervisor blocks the write. Other examples of embedded Hypervisor managed resources are
high- and low-speed peripheral interfaces (PCIe, UART) if those resources are not dedicated to a
single CPU/partition.
3.10.3 Peripheral Access Management Unit (PAMU)
The P5020 includes a distributed function collectively referred to as the peripheral access management unit
(PAMU), which provides address translation and access control for all bus masters in the system (PME,
SEC, FMan, and so on). The PAMU access control can be one of the following:
• Absolute—The FMan, PME, SEC, and other bus masters can never access memory range XYZ.
• Conditional—Based on the Partition ID of the CPU that programmed the bus master
Being MMU-based, the embedded Hypervisor is only able to stop unauthorized software access attempts.
Internal components with bus mastering capability also need to be prevented from reading and writing to
specific memory regions. These devices do not spontaneously generate access attempts, but, if
programmed to do so by buggy or malicious software, any of them could overwrite sensitive configuration
registers and crash the system.
3.10.4 Secure Boot and Sensitive Data Protection
The core MMUs and PAMU allow the device to enforce a consistent set of memory access permissions on
a per-partition basis. When combined with embedded Hypervisor for safe sharing of resources, the P5020
becomes highly resilient when poorly tested or malicious code is run. For system developers building high
reliability/high security platforms, rigorous testing of code of known origin is the norm.
P5020 QorIQ Communications Processor Product Brief, Rev. 1
Features
Freescale Semiconductor26
3.10.4.1 Secure Boot Option
The system developer digitally signs the code to be executed by the CPU coming out of reset, and the
device ensures that only an unaltered version of that code runs on the platform. The P5020 offers both boot
time and run time code authenticity checking and configurable consequences when the authenticity check
fails.
3.10.4.2 Sensitive Data Protection Option
The P5020 supports protected internal and external storage of developer-provisioned sensitive instructions
and data.
For example, a system developer may provision each system with a number of RSA private keys to be used
in mutual authentication and key exchange. These values would initially be stored in external non-volatile
memory, but following secure boot, these values can be decrypted into on-chip protected memory (portion
of platform cache dedicated as SRAM). Session keys, which may number in the thousands to tens of
thousands, are not good candidates for on-chip storage, so the device offers session key encryption.
Session keys are stored in main memory, and are decrypted (transparently to software and without
impacting SEC throughput) as they are brought into the SEC 4.2 for decryption of session traffic.
3.11 Advanced Power Management
The P5020’s advanced power management capabilities are based around fine-grained static clock control
and software-controlled dynamic frequency management.
3.11.1 Saving Power by Managing Internal Clocks
Dynamic voltage and frequency scaling (DVFS) are useful techniques for reducing typical/average power
and maximizing battery life in laptop environments, but embedded applications must be designed for rapid
response to bursts of traffic and max power under worst-case environmental conditions. While the P5020
does not implement DVFS in the PC sense, it does actively manage internal clocks to avoid wasting energy.
Clock signals are disabled to idle components, reducing dynamic power. These blocks can return to full
operating frequency on the clock cycle after work is dispatched to them.
The P5020 also supports (under software control) dynamic changes to CPU operating frequencies and
voltages. Each CPU sources its input clock from one of two independent PLLs inside the device. Each CPU
can also source its input clock from an integer frequency divider from two of the three independent PLLs.
CPUs can switch their source PLL, and their frequency divider glitchlessly and nearly instantaneously.
This allows each core to operate at the minimum frequency required to perform its assigned function,
saving power.
3.11.2 Turning Off Unneeded Clocks
Fine-grained static control allows developers to turn off the clocks to individual logic blocks within the
SoC that the system has no need for. Based on a finite number of SerDes, it is expected that any given
application will have some Ethernet MACs, PCIe, or Serial RapidIO controllers inactive. These blocks can
Features
P5020 QorIQ Communications Processor Product Brief, Rev. 1
Freescale Semiconductor 27
be disabled by means of the DEVDIS register. Re-enabling clocks to a logic block requires an SoC reset,
which makes this type of power management operation infrequent (effectively static).
3.11.3 Avoiding Full System Failure Due to Thermal Overload
Changing PLL frequency dividers (/2, /4) can be used to achieve large and rapid reductions in dynamic
power consumptions, and with the help of external temperature detection circuitry, can serve as a thermal
overload protection scheme. If the junction temperature or system ambient temperature of the device
achieves some critical level, external temperature detection circuitry can drive a high-priority interrupt into
the P5020, causing it to reduce selected CPU frequencies by half or more. This allows the system to
continue to function in a degraded mode, rather than failing entirely. This technique is much simpler than
turning off selected CPUs, which can involve complex task migration in an AMP system. When system
temperatures have been restored to safe ranges, all CPUs can be returned to normal frequency within a few
clock cycles.
When less drastic frequency changes are desired, software can switch the CPU to a slower speed PLL, such
as 1 G Hz versus 1.5 GHz. Many cores could be switched to a slower PLL during periods of light traffic,
with the ability to immediately return those cores to the full rate PLL should traffic suddenly increase. The
more traditional Power Architecture single-core power management modes (such as Core Doze, Core Nap,
and Core Sleep) are also available in the core.
3.12 Debug Support
The reduced number of external buses enabled by the move to multicore SoCs greatly simplifies board
level lay-out and eliminates many concerns over signal integrity. While the board designer may embrace
multicore CPUs, software engineers have real concerns over the potential to lose debug visibility. Despite
the problems external buses can cause for the HW engineer, they provide software developers with the
ultimate confirmation that the proper instructions and data are passing between processing elements.
Processing on a multicore SOC with shared caches and peripherals also leads to greater concurrency and
an increased potential for unintended CPU interactions. To ensure that software developers have the same
or better visibility into the P5020 as they would with multiple discrete Freescale communications
processors, Freescale developed the debug architecture shown in the following figure.
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P5020NXE1TNB

Mfr. #:
Buy P5020NXE1TNB
Manufacturer:
NXP / Freescale
Description:
Microprocessors - MPU P5020 ExtTmpEnc 1800/1333 r2.0
Lifecycle:
New from this manufacturer.
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