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P5020NXE1TNB

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Document Revision History
P5020 QorIQ Communications Processor Product Brief, Rev. 1
Freescale Semiconductor 31
• Global visibility
• Determinism
• Bug reproducibility
• Reverse execution
• Special abilities to detect race conditions
• Ability to detect race conditions
4.3.2 Hypervisor Micro-Kernel
The P5020’s e5500 cores offer a new embedded Hypervisor capability to address the need for a single
operating system performing coordination and access control functions, managing shared resources in an
efficient manner. The embedded Hypervisor provides the software layer needed to manage the operating
systems and supervisor-level applications as they access shared resources. Recognizing that each
developer’s system design may call for a different partitioning of resources, and involve different
combinations of OSes and RTOSes, Freescale and our ecosystem partners will provide reference
implementations of the embedded Hypervisor’s peripheral virtualization and access control which the
developer can modify to match unique system requirements.
4.3.3 DPAA Reference “Stacklets”
It is expected that some CPUs will be dedicated as datapath processors, working closely with the DPAA.
Freescale will provide reference protocol “stacklets,” optimizing performance critical regions of protocol
processing and their interaction with the DPAA hardware.
4.4 Top Level of the Pyramid: Application-Specific Enablement
This category includes 3rd-party stacks optimized for DPAA, RegEx, AV TCP, IPv4/6, IPsec/SSL.
Many of the expected applications for the P5020 involve network protocol processing. Partitioning
between control CPUs and datapath CPUs, and developing the protocol processing firmware which runs
on the datapath CPUs is an area for significant value added services for Freescale partners at the top level
of the enablement pyramid. OEMs wishing to engage with these partners can realize significant
“time-to-performance” advantages.
5 Document Revision History
The following table provides a revision history for this product brief.
Table 8. Revision History
Revision Date Substantive Change(s)
1 02/2013 Modified USB Specification, Section 3.7, “Universal Serial Bus (USB) 2.0.”
0 12/2011 Initial public release.
Document Number: P5020PB
Rev. 1
02/2013
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Freescale, the Freescale logo, AltiVec, C-5, CodeTest, CodeWarrior, ColdFire, C-Ware,
Energy Efficient Solutions logo, Kinetis, mobileGT, PowerQUICC, Processor Expert,
QorIQ, Qorivva, StarCore, Symphony, and VortiQa are trademarks of Freescale
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© 2011-2013 Freescale Semiconductor, Inc.
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P5020NXE1TNB

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Microprocessors - MPU P5020 ExtTmpEnc 1800/1333 r2.0
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