NCV7381
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19
Table 24. TxD PIN PARAMETERS
Symbol Parameter Conditions Min Typ Max Unit
uBDLogic_0 Low level input voltage −0.3 0.4*V
io
V
uBDLogic_1 High level input voltage 0.6*V
io
5.5 V
R
PD
_TxD Pull−down resistance 5 11 20
kW
C_BDTxD Input capacitance on TxD pin (Note 14) f = 5 MHz 10 pF
iTxD
LI
Low level input current uTXD = 0 V −1 0 1
mA
14.Values based on design and characterization, not tested in production
Table 25. TxEN PIN PARAMETERS
Symbol Parameter Conditions Min Typ Max Unit
R
PU
_TxEN Pull−up resistance 50 110 200
kW
iTxEN
IH
High level input current uTXEN = V
IO
−1 0 1
mA
iTxEN
LEAK
Input leakage current uTxEN = 5.25 V, V
IO
= 0 V −1 0 1
mA
Digital Output Signals
Table 26. DIGITAL OUTPUT SIGNALS VOLTAGE LIMITS (Pins RXD, RxEN and ERRN)
Symbol Parameter Conditions Min Typ Max Unit
uV
DIG−OUT−LOW
Low level output voltage iRxD
OL
= 6 mA
iRxEN
OL
= 5 mA
iERRN
OL
= 0.7 mA
(Note 15)
0 0.2*V
IO
V
uV
DIG−OUT−HIGH
High level output voltage iRxD
OH
= −6 mA
iRxEN
OH
= −5 mA
iERRN
OH
= −0.7 mA
(Note 15)
0.8*V
IO
V
IO
V
uV
DIG−OUT−UV
Output voltage on a digital output when
V
IO
in undervoltage
R
LOAD
= 100 kW to GND,
Either V
CC
or V
BAT
supplied
500 mV
uV
DIG−OUT−OFF
Output voltage on a digital output when
unsupplied
R
LOAD
= 100 kW to GND
500 mV
15.uVDIG = uVIO. No undervoltage on VIO and either VCC or VBAT supplied.
Table 27. RxD PIN PARAMETERS
Symbol Parameter Conditions Min Typ Max Unit
dBDRxD
R15
RXD signal rise time (20%−80% V
IO
)
RxD pin loaded with
15 pF capacitor
(Note 16)
6.5 ns
dBDRxD
F15
RXD signal fall time (20%−80% V
IO
) 6.5 ns
dBDRxD
R15
+
dBDRxD
F15
Sum of rise and fall time
(20%−80% V
IO
)
13 ns
|dBDRxD
R15
−
dBDRxD
F15
|
Difference of rise and fall time 5 ns
dBDRxD
R25
RXD signal rise time (20%−80% V
IO
)
RxD pin loaded with
25 pF capacitor
8.5 ns
dBDRxD
F25
RXD signal fall time (20%−80% V
IO
) 8.5 ns
dBDRxD
R25
+
dBDRxD
F25
Sum of rise and fall time
(20%−80% V
IO
)
16.5 ns
|dBDRxD
R25
−
dBDRxD
F25
|
Difference of rise and fall time 5 ns
dBDRxD
R25_10
+
dBDRxD
F25_10
RXD signal sum of rise and fall time at
TP4_CC (20%−80% V
IO
)
RxD pin loaded with 25 pF
capacitor plus 10 pF at the
end of a 50 W, 1 ns
microstripline
(Note 17)
16.5 ns
|dBDRxD
R25_10
−
dBDRxD
F25_10
|
RXD signal difference of rise and fall
time at TP4_CC (20%−80% V
IO
)
5 ns
16.Values based on design and characterization, not tested in production
17.Simulation result. Simulation performed within T
J_OP
range, according to FlexRay Electrical Physical Layer Specification, Version 3.0.1
