NCV7381DP0R2G Datasheet NCV7381DP0R2G, NCV7381DP0G | P7-P9

NCV7381

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Operating Mode Changes Caused by Internal Flags

Changes of some internal flags described in Table 3 can

force an operating mode transition complementing or

overruling the operating mode control by the digital inputs

STBN and EN which is shown in Figure 3:

• Setting the V

BAT

or V

under−voltage flag causes a

transition to the Sleep mode

• Setting the V

under−voltage flag, while the bus driver

is not in Sleep, causes a transition to the Standby mode

• Reset of the Under−voltage flag (i.e. recovery from

under−voltage) re−enables the control of the chip by

digital inputs STBN and EN.

• Setting of the Wake flag causes the reset of all

under−voltage flags and the NCV7381 transitions to the

Standby mode. The reset of the under−voltage flags

allows the external power supplies to stabilize properly

if, for example, they were previously switched off

during Sleep mode.

FlexRay Bus Driver

NCV7381 contains a fully−featured FlexRay bus driver

compliant with Electrical Physical Layer Specification Rev.

3.0.1. The transmitter part translates logical signals on

digital inputs TxEN, BGE and TxD into appropriate bus

levels on pins BP and BM. A transmission cannot be started

with Data_1. In case the transmitter is enabled for longer

than dBDTxActiveMax, the TxEN Timeout flag is set and the

current transmission is disabled. The receiver part monitors

bus pins BP and BM and signals the detected levels on digital

outputs RxD and RxEN. The different bus levels are defined

in Figure 5. The function of the bus driver and the related

digital pins in different operating modes is detailed in

Table 4 and Table 5.

• The transmitter can only be enabled if the activation of

the transmitter is initiated in Normal mode.

• The receiver function is enabled by entering a

normal−power mode.

Idle_LP

Idle

Data_0 Data_1

Figure 5. FlexRay Bus Signals

uBus

Table 4. TRANSMITTER FUNCTION AND TRANSMITTER−RELATED PINS

Operating Mode BGE TxEN TxD Transmitted Bus Signal

Standby, Go−to−sleep, Sleep x x x Idle_LP

Receive−only x x x Idle

Normal

0 x x Idle

1 1 x Idle

1 0 0 Data_0

1 0 1 Data_1

Table 5. RECEIVER FUNCTION AND RECEIVER−RELATED PINS

Operating Mode Signal on Bus Wake flag RxD RxEN

Standby, Go−to−sleep, Sleep

x not set High High

x set Low Low

Normal,

Receive−only

Idle x High High

Data_0 x Low Low

Data_1 x High Low

NCV7381

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Bus Guardian Interface

The interface consists of the BGE digital input signal

allowing a Bus Guardian unit to disable the transmitter and

of the RxEN digital output signal used to signal whether the

communication signal is Idle or not.

Bus Driver Voltage Regulator Control

NCV7381 provides a high−voltage output pin INH which

can be used to control an external voltage regulator (see

Figure 2). The pin INH is driven by a switch to V

BAT

supply.

In Normal, Receive−only, Standby and Go−to−Sleep modes,

the switch is activated thus forcing a High level on pin INH.

In the Sleep mode, the switch is open and INH pin remains

floating. If a regulator is directly controlled by INH, it is

then active in all operating modes with the exception of the

Sleep mode.

Bus Driver Remote Wakeup Detection

During a low−power mode and under the presence of

BAT

voltage, a low−power receiver constantly monitors the

activity on bus pins BP and BM. A valid remote wake−up is

detected when either a wakeup pattern or a dedicated

wakeup frame is received. A valid remote wake−up is also

detected when wake−up pattern has been started in

normal−power mode already.

A wakeup pattern is composed of two Data_0 symbols

separated by Data_1 or Idle symbols. The basic wakeup

pattern composed of Data_0 and Idle symbols is shown in

Figure 6; the wakeup pattern composed of Data_0 and

Data_1 symbols – referred to as “alternative wakeup

pattern” − is depicted in Figure 7.

Idle(_LP) Data_0 Idle(_LP) Data_0 Idle(_LP)

Figure 6. Valid Remote Wakeup Pattern

detected

Remote wakeup

uBus

uData0_LP

<dWU

Timeout

>dWU

0Detect

>dWU

IdleDetect

>dWU

0Detect

>dWU

IdleDetect

Figure 7. Valid Alternative Remote Wakeup Pattern

Idle(_LP) Data_0 Data_1 Data_0

detected

Remote wakeup

uBus

uData0_LP

<dWU

Timeout

>dWU

0Detect

>dWU

IdleDetect

>dWU

0Detect

>dWU

IdleDetect

Data_1

A remote wakeup will be also detected if NCV7381 receives a full FlexRay frame at 10 Mbit/s with the following payload data:

0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00,

0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF

The wakeup pattern, the alternative wakeup pattern and the wakeup frame lead to identical wakeup treatment and signaling.

Local Wakeup Detection

The high−voltage input WAKE is monitored in

low−power modes and under the condition of sufficient

BAT

supply level. If a falling edge is recognized on WAKE

pin, a local wakeup is detected. In order to avoid false

wakeups, the Low level after the falling edge must be longer

than dWakePulseFilter in order for the wakeup to be valid.

The WAKE pin can be used, for example, for switch or

contact monitoring.

Internal pull−up and pull−down current sources are

connected to WAKE pin in order to minimize the risk of

parasitic toggling. The current source polarity is

automatically selected based on the WAKE input signal

polarity – when the voltage on WAKE stays stable High

(Low) for longer than dWakePulseFilter, the internal current

source is switched to pull−up (pull−down).

NCV7381

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ERRN Pin and Status Register

Provided V

supply is present together with either V

BAT

or V

, the digital output ERRN indicates the state of the

internal “Error” flag when in Normal mode and the state of

the internal “Wake” flag when in Standby, Go−to−Sleep or

Sleep. In Receive−only mode ERRN indicates either the

state of the internal “Error” or the wakeup source (See

Table 6).

The polarity of the indication is reversed – ERRN pin is

pulled Low when the “Error” flag is set. The signaling on pin

ERRN functions in all operating modes.

Table 6. SIGNALING ON ERRN PIN

STBN EN Conditions Error flag Wake flag ERRN

High High −

not set x High

set x Low

High Low EN has been set to High after previous wakeup

not set x High

set x Low

EN has not been set to High after previous wakeup

x Set local High

x Set remote Low

Low x −

x not set High

x set Low

Additionally, a full set of internal bits referred to as status

a clock signal – the status register content is described in

Table 7 while an example of the read−out waveforms is

shown in Figure 8 and Figure 9. The individual status bits are

channeled to ERRN pin with reversed polarity (if a status bit

is set, ERRN is pulled Low) at the falling edge on EN pin (the

status register starts to be shifted only at the second falling

edge). As long as the EN pin toggling period falls in the

dEN

STAT

range, the operating mode is not changed and the

read−out continues. As soon as the EN level is stable for

more than dBDModeChange, the read−out is considered as

finished and the operating mode is changed according the

current EN value. At the same time, the status register bits

S4 to S10 are reset provided the particular bits have been

read−out and the corresponding flags are not set any more –

see Table 7. The status register read−out always starts with

bit S0 and the exact number of bits shifted to ERRN during

the read−out is not relevant.

Table 7. STATUS REGISTER

Bit Number Status Bit Content Note

Reset after Finished

Read−out

S0 Local wakeup flag

reflects directly the corresponding flag no

S1 Remote wakeup flag

S2 not used; always High no

S3 Power−on status

the status bit is set if the corresponding flag

was set previously (the respective High level of

the flag is latched in its status counter−part)

yes, if the

corresponding flag is

reset and the bit was

read−out

S4 Bus error status

S5 Thermal shutdown status

S6 Thermal warning status

S7 TxEN Timeout status

S8 V

BAT

Under−voltage status

S9 V

Under−voltage status

S10 V

Under−voltage status

S11 BGE Feedback Normal mode: BGE pin logical state (Note 3)

Other modes: Low

−

S12−S15 not used; always Low no

S16−S23 Version of the NCV7381 analog part

fixed values identifying the production masks

version

S24−S31 Version of the NCV7381 digital part

3. The BGE pin state is latched during status register read−out at rising edge of the EN pin.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24

NCV7381DP0R2G

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Manufacturer:

ON Semiconductor

Description:

Interface - Specialized CLAMP 30 FLEXRAY TRANSC.

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NCV7381DP0R2G

NCV7381DP0R2G

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