SiC530
www.vishay.com
Vishay Siliconix
S15-2523-Rev. B, 02-Nov-15
10
Document Number: 62940
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
PCB LAYOUT RECOMMENDATIONS
Step 1: V
IN
/ P
GND
Planes and Decoupling
1. Layout V
IN
and P
GND
planes as shown above.
2. Ceramic capacitors should be placed directly between
V
IN
and P
GND
, and close to the device for best
decoupling effect.
3. Different values / packages of ceramic capacitors should
be used to cover entire decoupling spectrum e.g. 1210,
0805, 0603, 0402.
4. Smaller capacitance values, placed closer to the device’s
V
IN
pin(s), results in better high frequency noise
absorbing.
Step 2: V
SWH
Plane
1. Connect output inductor to IC with large plane to lower
resistance.
2. V
SWH
plane also serves as a heat-sink for low-side
MOSFET. Make the plane wide and short to achieve the
best thermal path.
3. If a snubber network is required, place the components
as shown above, the network can be placed at bottom.
Step 3: V
CIN
/ V
DRV
Input Filter
1. The V
CIN
/ V
DRV
input filter ceramic cap should be placed
as close as possible to the IC. It is recommended to
connect two capacitors separately.
2. V
CIN
capacitor should be placed between pin 2 (V
CIN
) and
pin 3 (A
GND
of driver IC) to achieve best noise filtering.
3. V
DRV
capacitor should be placed between pin 20
(P
GND
of driver IC) and pin 21 (V
DRV
) to provide maximum
instantaneous driver current for low side MOSFET during
switching cycle.
4. For connecting V
CIN
to A
GND
, it is recommended to use
a large plane to reduce parasitic inductance.
Step 4: BOOT Resistor and Capacitor Placement
1. The components need to be placed as close as possible
to IC, directly between PHASE (pin 5) and BOOT (pin 4).
2. To reduce parasitic inductance, chip size 0402 can be
used.
V
IN
V
SWH
P
GND
V
IN
Pl ane
P
GND
Pl ane
P
GND
Plane
V
SWH
Snubber
P
GND
C
vcin
C
vdrv
A
GND
