LTC1699 Series
11
APPLICATIO S I FOR ATIO
WUU
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output voltage of a DC/DC converter that generates the
CPU core supply voltage. Its programmable ratios (see
Table 1) are designed for 0.8V-referenced converters such
as the LTC1628, LTC1702, LTC1735 and LTC1778 and
comply with the Intel 5-bit desktop (VRM8.4 for
LTC1699-81 and VRM9.0 for LTC1699-82) and 5-bit
mobile VID codes. On power-up, the outputs of both
registers are internally set to 11111B.
The LTC1699-80, LTC1699-81 and LTC1699-82 provide
three pins, CPU_ON, IO_ON, and CLK_ON to (optionally)
control three DC/DC converters that generate the CPU, I/O
and clock buffer V
CC
voltages in a VRM. These open drain,
N-channel output pins usually connect to the RUN/SS pins
of the converters and pull low to shut down the converters
or become a high impedance state to allow the converters
to soft-start.
The PGOOD pin is driven from an internal timer that pulls
PGOOD low for 50µs typical whenever the resistor divider
setting is changed or the converters are allowed to soft-
start. Over the entire temperature and supply voltage
range, the timer low period is 70µs max which meets the
100µs max converter output settling time specified by
Intel. The PGOOD pin, if tied to the FCB pin of an LTC DC/
DC converter, reduces the time needed for the converter
output to decrease to a lower voltage under light load
conditions by forcing the converter into continuous mode
for 50µs.
The TTL compatible VRON input pin and the output of the
internal on/off state machine (SMBON) control the state of
the CPU_ON, IO_ON, CLK_ON and PGOOD pins. SMBON
is accessed using SMBus protocols and must be pro-
grammed to a high state before the converters can turn on.
The SMBus protocols (see Figure 2) incorporate safe-
guards against errors caused by bus conflicts.
Resistor Divider
The resistor divider is designed specifically for DC/DC
converters, such as the LTC1628, LTC1702, LTC1735,
LTC1778 and LTC1929 with a reference voltage of 0.8V. It
consists of a fixed resistor, R
FB1
connected between the
SENSE and FB pins and a variable resistor, R
FB2
, con-
nected between the FB and GND pins. The SENSE and FB
pins are tied to the output and feedback nodes of the DC/
DC converter respectively. The output of the DC/DC con-
verter is given by:
V
OUT
= V
REF
• (R
FB2
+R
FB1
)/R
FB2
where V
REF
is the internal reference voltage of the con-
verter. Each resistor has a tolerance of ±30% but the ratio,
(R
FB2
+R
FB1
)/R
FB2
, is specified to within ±0.35% over
temperature. The error budget for the DC/DC converter
output voltage must include the ±0.35% ratio tolerance
and the tolerance in V
REF
.
The value of R
FB1
is fixed and R
FB2
is changed to vary the
divider setting. The value of R
FB2
for any divider setting
can be calculated from the above equation, assuming that
R
FB1
= 10kΩ for the LTC1699-80 and LTC1699-82 and
20kΩ for the LTC1699-81. Table 1 shows the output
voltage of a DC/DC converter (V
REF
= 0.8V) for all 32
settings of the resistor divider. The divider setting is
determined by the outputs (VID0-VID4) of the register
selected by the SEL pin.
SMBus Interface
The SMBus interface uses two wires: SDA and SCL. Data
to the LTC1699-80, LTC1699-81 or LTC1699-82, is latched
at the rising edge of the SCL clock input and shifted out at
the falling edge. The V
IL
and V
IH
logic threshold voltages
of the SDA and SCL pins are 0.8V and 2.1V respectively
and comply with Rev 1.1 version of the Intel System
Management Bus Specifications.
The Write Word and Read Word protocols (Figure 2) share
three common features. First, the 7-bit slave address for
both protocols is internally hardwired to 1110 001B = E2H.
A single R/W bit follows the slave address. This bit is low
for data transfer from the microprocessor to the LTC1699-
80, LTC1699-81 or LTC1699-82 and high for transfers in
the opposite direction.
Second, the LTC1699-80, LTC1699-81 and LTC1699-82
decode only the three most significant bits of the 8-bit
command code. Table 2 shows the four valid combina-
tions. All other combinations are ignored.
Third, the Data Low and Data High bytes correspond to
Registers 0 and 1 respectively. In Write Word protocol with
C7 = C6 = 0, C5 = 1, the five most significant bits (VID0-
VID4) of these bytes specify a resistor divider setting.
