LTC1699EMS8-81#TRPBF Datasheet LTC1699EGN-82#PBF, LTC1699EGN-80#PBF, LTC1699EGN-81#PBF | P13-P15

LTC1699 Series

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the SMBus interface returns to an idle state and waits for

the next start bit.

Read Word Protocol

The Read Word protocol starts off like Write Word proto-

col but after the command code acknowledgment, the

microprocessor issues a second start bit (called a re-

peated start). This is followed by the slave address but with

the R/W bit set high to indicate that data direction is now

from the LTC1699-80, LTC1699-81 or LTC1699-82 to the

microprocessor. The LTC1699-80, LTC1699-81 or

LTC1699-82 then acknowledges the slave address and

clocks the contents of Register 0 (Data Low byte) to the

microprocessor. The Data Low byte is acknowledged by

the microprocessor. On detecting the acknowledgment

bit, the LTC1699-80, LTC1699-81 or LTC1699-82 clocks

out the contents of Register 1 (Data High byte). As defined

in the SMBus specifications, the microprocessor does not

acknowledge the last data byte. The LTC1699-80,

LTC1699-81 or LTC1699-82 enters an idle state to wait for

the next start bit after clocking out the Data High byte. The

five most significant bits (VID0-VID4) of the Data Low and

High bytes are the resistor divider settings previously

loaded using the Setup protocol. The next bit below the

VID0-VID4 bits is the status of the DCON signal. If this bit

is low (high), the DC/DC converters are switched on (off).

The two unused, least significant bits of the Data Low and

Data High bytes are clocked out as zeros which removes

the need to mask out these bits in software.

Safeguards

The LTC1699-80, LTC1699-81 and LTC1699-82 provide

safeguards against incorrect divider codes and the unin-

tentional turn-on or turn-off of the DC/DC converters.

Incorrect codes due to bus conflicts during Setup proto-

cols can cause damage to circuits powered by the DC/DC

converters. The safeguards built into the LTC1699-80,

LTC1699-81 and LTC1699-82 include Read-Back, re-

peated On and Off protocols, ignoring On protocols if the

registers have not been setup, locking out registers while

the DC/DC converters are operating and latching in VID

codes only in Setup protocols.

After power-up, the microprocessor must set up the

registers before the LTC1699-80, LTC1699-81 and

LTC1699-82 recognizes On protocols. This requirement

ensures that the correct DC/DC converter output is pro-

grammed before the converters are turned on. After setup,

Read-Back allows the contents of Registers 0 and 1 to be

verified in case the VID codes were corrupted by noise or

bus conflicts.

In order to turn on the DC/DC converter, two On protocols

must be sent to slave address E2H without any other (E2H)

protocols in between. Protocols to other slave addresses

are still allowed and are ignored. Similarly, two Off proto-

cols must be sent to slave address E2H to turn the

converters off. The On and Off protocols are monitored by

an internal state machine. The output of the state machine,

SMBON, is high after two On commands and low after two

Off commands. Repeated On and Off protocols reduce the

chances of bus conflicts and noise turning the converter

on or off accidentally. In both On and Off protocols, the

LTC1699-80, LTC1699-81 and LTC1699-82, do not latch

in the Data Low and Data High bytes. This protects the

settings that have already been loaded into the registers

and verified by read-back.

Once the converters are turned on (both SMBON and

VRON are high) the contents of Registers 0 and 1 are

protected and can only be altered with Setup protocols if

VRON is pulled low or two Off protocols are sent to the

LTC1699-80, LTC1699-81 or LTC1699-82 (to force SMBON

low).

DC/DC Converter Control

The LTC1699-80, LTC1699-81 and LTC1699-82 provide

six pins for DC/DC converter control: SEL, VRON, CPU_ON,

IO_ON, CLK_ON and PGOOD. These pins (except SEL) and

the output of the internal on/off state machine (SMBON)

determine if the DC/DC converters are operating or in

shutdown.

The SEL and VRON pins are TTL compatible, high imped-

ance inputs with a logic threshold of 1.3V over the entire

2.7V to 5.5V supply range. They are compatible with 3.3V

logic and have ±50mV of hysterisis for noise rejection.

When pulled high or low, the SEL pin selects Register 1

and 0 respectively as the active divider setting. The VRON

LTC1699 Series

pin is used to shut down the converters without the need

for lengthy SMBus Off protocols and can also be used to

turn on up to three DC/DC converters simultaneously. The

VRON pin has an internal 2.5uA current source pull-up.

The CPU_ON, IO_ON and CLK_ON pins are N-channel,

open drain outputs. These outputs can be connected to the

RUN/SS pin of LTC DC/DC converters that generate the

supplies of the CPU, I/O circuits and the clock buffer.

The RUN/SS pin shuts down the converter if pulled low

and also serves as a connection for the soft-start capaci-

tor. The CPU_ON, IO_ON and CLK_ON pins are open drain

outputs and do not interfere with soft-start when switched

into a high impedance state. To keep the I/O and clock

buffer V

supplies alive at all times, disconnect the IO_ON

and CLK_ON pins from the corresponding RUN/SS pins.

The N-channel FETs at the CPU_ON, IO_ON and CLK_ON

pins typically discharge a 0.1µF (0.01µF) soft-start capaci-

tor from 3V to 0.35V in 21µs (2.3µs) with V

= 2.7V.

The PGOOD or “Power Good” pin is also an open drain,

N-channel output. The PGOOD pin pulls low if the DC/DC

converters are shutdown. If the converters are turned on,

an internal timer keeps PGOOD low for 50µs (typical)

which allows time for the converters to enter regulation.

Toggling the SEL pin while the converters are turned on

also causes the PGOOD pin to pull low for 50µs. The

PGOOD pin may be used to force continuous operation in

an LTC DC/DC converter. If the SEL pin is toggled to select

a lower output voltage, it may take an unacceptably long

time for the output of the DC/DC converter to decrease to

the new voltage under light load conditions. To reduce this

time needed, the PGOOD pin can be connected to the FCB

(force continuous bar) pin of the converter. When the SEL

pin is toggled to select a new code, FCB pin is forced low

for 50µs. This forces the DC/DC converter out of Burst

Mode

operation and into continuous mode.

The VRON pin and SMBON, the output of the internal on/

off state machine, control the state of the CPU_ON, IO_ON,

CLK_ON and PGOOD pins. The DCON signal is a logical

NAND function of the logical states of VRON and SMBON

and is the status bit that is returned during Read-back.

Table␣ 3 shows the state of the CPU_ON, IO_ON, and

CLK_ON pins for various combinations of VRON and

SMBON.

Table 3. DC/DC Converter Control Pins

VRON SMBON DCON PGOOD CPU_ON, IO_ON, CLK_ON

0X10 0

(Note 3)

1010 0

1 ↑↓0 for 50µs Z (Note 2)

(Note 1)

↑ 1 ↓ 0 for 50µs Z (Note 2)

(Note 1)

Note 1: Also triggered by SEL pin toggling.

Note 2: Z = High Impedance

Note 3: X = Don’t care

If the DCON control bit goes high, the N-channel transistor

at the CPU_ON, IO_ON, CLK_ON and PGOOD pins turn on,

pulling these pins to ground. Any connected RUN/SS pins

are pulled to ground, shutting down the converters.

If the DCON control bit goes low, the N-channel transistor

at the CPU_ON, CLK_ON, IO_ON and PGOOD pins turn off

and become high impedance outputs. This allows the soft-

start capacitor at each RUN/SS pin to charge up and the

DC/DC converters wake up gradually with a soft-start

cycle. The PGOOD pin also pulls low for typically 50µs to

indicate that the converter outputs are temporarily out of

regulation. An internal timer determines the duration of

the low pulse. The timer is triggered by SEL toggling or

DCON going low.

Power-Up Reset

On power-up, the internal POR circuit generates a low

reset pulse, which stays low until V

rises above approxi-

mately 2.2V. The reset pulse forces the SMBus interface

into an idle state in which it listens for a start bit. At the

same time the outputs of both Register 0 and Register 1

are set to 11111B. The DCON bit is pulled high so that the

CPU_ON, IO_ON, CLK_ON and PGOOD pins are pulled low

to shut down the DC/DC converters.

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Burst Mode is a trademark of Linear Technology Corporation.

LTC1699 Series

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Operating Sequence

A typical control sequence for the LTC1699-80,

LTC1699-81 and LTC1699-82 is as follows:

• On power up, the DCON bit is preset to a high state by

the power-on reset (POR) circuit. The CPU_ON, IO_ON

and CLK_ON pins are pulled low to shut down the DC/

DC converters. PGOOD pulls low to indicate that the

converters are not in regulation.

• Pull VRON low as a precaution. Take SEL high or low to

select the divider setting; e.g., one that suits the existing

power source (battery or wall-pack).

• Use the Setup protocol to load the appropriate divider

settings in Registers 0 and 1 and enable the on/off state

machine.

• Use the Read-Back protocol to verify the contents of

Registers 0 and 1.

• Repeat the setup and read-back if the codes are incor-

rect (due to bus conflicts).

• Send two On protocols in succession to clear the DCON

bit.

• Use the Read-Back protocol to verify that the DCON is

low. A high state will indicate that an On command code

was corrupted by bus conflicts.

• Pull VRON high. Since DCON = 0, the CPU_ON, IO_ON

and CLK_ON pins enter a high impedance state, allow-

ing the DC/DC converters to soft-start. PGOOD stays

low for 50µs.

• To shut down the supply, send two Off protocols to set

the DCON bit high or pull VRON low if immediate

shutdown is required.

The VRON signal in the 8-pin MSOP versions of the

LTC1699-80, LTC1699-81 and LTC1699-82 are pulled

high internally by a 2.5µA current source. For these

versions, the converters are turned on or off only through

the SMBus interface.

Overvoltage Protection Faults

Toggling the SEL pin, i.e. changing the ladder setting “on

the fly” can trigger some converters with over-voltage

fault protection (OVP) into a fault state if the new setting

calls for a lower output voltage. For some converters such

as the LTC1702, cycling the power supply is the only way

to clear the fault and restore normal operation.

For the LTC1702, an OVP fault is triggered if the difference

between the programmed and prevailing output voltages

is greater than 15%, and persists for more than 25µs. To

prevent the OVP fault from disabling the LTC1702, tie the

FAULT pin of the LTC1702 low. Tying FAULT low does not

disable the OVP circuit but blocks its effects.

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