Z87200
Spread-Spectrum Transceiver Zilog
4-17
The Z87200 contains a fully programmable 64-tap com-
plex (dual I and Q channel) PN Matched Filter with coeffi-
cients which can be set to ±1 or zero according to the con-
tents of either the Acquisition/Preamble or Data Symbol
Code Coefficient Registers. By setting the coefficients of
the end taps of the filter to zero, the effective length of the
filter can be reduced for use with PN codes shorter than 64
bits. Power consumption may also be reduced by turning
off those blocks of 7 taps for which all the coefficients are
zero, using bits 6-0 of address 39H. Each ternary coeffi-
cient is stored as a 2-bit number so that a PN code of
length N is stored as N 2-bit non-zero PN coefficients. Note
that, as a convention, throughout this document the first
PN Matched Filter tap encountered by the signal as it en-
ters the I and Q channel tapped delay lines is referred to
as “Tap 0.” Tap 63 is then the last tap of the PN Matched
Filter.
The start of each burst is expected to be a single symbol
PN-spread by the Acquisition/Preamble code. The receiv-
er section of the Z87200 is automatically configured into
acquisition mode so that the Matched Filter Acquisi-
tion/Preamble Coefficients stored in addresses 07
H
to 16
H
are used to despread the received signal. Provided that
this symbol is successfully detected, the receiver will auto-
matically switch from acquisition mode, and the Matched
Filter Data Symbol Coefficients stored in addresses 17
H
to
26
H
will then be used to despread subsequent symbols.
To allow the system to sample the incoming signal asyn-
chronously (at the I.F. sampling rate) with respect to the
PN spreading rate, the PN Matched Filter is designed to
operate with two signal samples (at the baseband sam-
pling rate) per chip. A front end processor (FEP) operating
on both the I and Q channels averages the incoming data
over each chip period by adding each incoming baseband
sample to the previous one:
FEP
OUT
= FEP
IN
(1 + z
–1
)
After the addition, the output of the FEP is rounded to a 3-
bit offset 2’s complement word with an effective range of
±3.5 such that the rounding process does not introduce
any bias to the data. The FEP can be disabled by setting
bit 0 of address 27
H
to 1, but for normal operation the FEP
should be enabled.
The PN Matched Filter computes the cross-correlation be-
tween the I and Q channel signals and the locally stored
PN code coefficients at the baseband sampling rate, which
is twice per chip. The 3-bit signals from each tap in the PN
Matched Filter are multiplied by the corresponding coeffi-
cient in two parallel tapped delay lines. Each delay line
consists of 64 multipliers which multiply the delayed
3-bit signals by zero or ±1 according to the value of the tap
coefficient. The products from the I and Q tapped delay
lines are added together in the I and Q Adders to form the
sums of the products, representing the complex cross-cor-
relation factor. The correlation I and Q outputs are thus:
n = 63
Output
(I, Q)
=Σ Data
n(I, Q)
* Coefficient
n(I, Q)
n = 0
These I and Q channel PN Matched Filter outputs are 10-
bit signals, with I and Q channel programmable viewports
provided to select the appropriate output bits as the 8-bit
inputs to the Power Detector and DPSK Demodulator
blocks. Both I and Q channel viewports are jointly con-
trolled by the data stored in bits 1-0 of address 28
H
and are
saturation protected.
Two power saving methods are used in the PN Matched
Filter of the Z87200. As discussed previously, the first
method allows power to be shut off in the unused taps of
the PN Matched Filter when the filter length is configured
to be less than 64 taps. The second method is a propri-
etary technique that (transparently to the user) shuts down
the entire PN Matched Filter during portions of each sym-
bol period.
PS010202-0601
Z87200
Spread-Spectrum Transceiver Zilog
4-18
FUNCTIONAL BLOCKS (Continued)
Power Detector
The complex output of the PN Matched Filter is fed into a
Power Detector which, for every cycle of the internal base-
band sampling clock, computes the magnitude of the vec-
tor of the I and Q channel correlation sums,
I
2
(K)+Q
2
(k), where the magnitude is approximated as
Max{Abs(I),Abs(Q)} + 1/2 Min{Abs(I), Abs(Q)}.
This 10-bit value represents the power level of the corre-
lated signal during each chip period and is used in the
Symbol Tracking Processor.
Symbol Tracking Processor
The output of the Power Detector Block represents the sig-
nal power during each chip period. Ideally, this output will
have a high peak value once per symbol (that is, once per
PN code cycle) when the code sequence of the received
signal in the PN Matched Filter is the same as (and is
aligned in time with) the reference PN code used in the PN
Matched Filter. At that instant, the I and Q channel outputs
of the PN Matched Filter are, theoretically, the optimally
despread I and Q symbols.
Figure 7. PN Matched Filter
PS010202-0601
Z87200
Zilog Spread-Spectrum Transceiver
4-19
4
To detect this maximum correlation in each symbol period,
the signal power value is compared against a 10-bit user-
programmable threshold value. A symbol clock pulse is
generated each time the power value exceeds the thresh-
old value to indicate a symbol detect. Since the Acquisi-
tion/Preamble symbol and subsequent data symbols can
have different PN codes with different peak correlation val-
ues (which depend on the PN code length and code prop-
erties), the Z87200 is equipped with two separate thresh-
old registers to store the Acquisition/Preamble Threshold
value (stored in addresses 29
H
and 2A
H
) and the Data
Symbol Threshold value (stored in addresses 2B
H
and
2C
H
). The device will automatically use the appropriate
value depending on whether it is in acquisition mode or
not.
Since spread-spectrum receivers are frequently designed
to operate under extremely adverse signal-to-noise ratio
conditions, the Z87200 is equipped with a “flywheel circuit”
to enhance the operation of the symbol tracking function
by introducing memory to the PN Matched Filter operation.
This circuit is designed to ignore false detects at inappro-
priate times in each symbol period and to insert a symbol
clock pulse at the appropriate time if the symbol detection
is missed. The flywheel circuit operates by its
a priori
knowledge of when the next detect pulse is expected.
A
priori
, the expected pulse will occur one symbol period af-
ter the last correctly detected one, and a window of ±1
baseband sample time is therefore used to gate the detect
pulse. Any detects generated outside this time window are
ignored, while a symbol detect pulse will be inserted into
the symbol clock stream if the power level does not exceed
the threshold within the window, corresponding to a
missed detect. An inserted symbol detect signal will be
generated precisely one symbol after the last valid detect,
the nominal symbol length being determined by the value
of Rx Chips Per Data Symbol stored in address 2D
H
.
The cross-correlation characteristics of a noisy received
signal with the noise-free local PN code used in the
Z87200’s PN Matched Filter may result in “smearing” of
the peak power value over adjacent chip periods. Such
smearing can result in two or three consecutive power val-
ues (typically, the on-time and one-sample early and late
values) exceeding the threshold. A maximum power selec-
tor circuit is incorporated in the Z87200 to choose the high-
est of any three consecutive power levels each time this
occurs, thereby enhancing the probability that the optimum
symbol timing will be chosen in such cases. If desired, this
function can be disabled by setting bit 3 of address 30
H
high.
The Z87200 also includes a circuit to keep track of missed
detects; that is, those cases where no peak power level ex-
ceeds the set threshold. An excessively high rate of
missed detects is an indication of poor signal quality and
can be used to abort the reception of a burst of data. The
number of symbols expected in each receive burst, up to a
maximum of 65,533, is stored in addresses 2E
H
and 30
H
.
A counter is used to count the number of missed detects in
each burst, and the system can be configured to automat-
ically abort a burst and return to acquisition mode if this
number exceeds the Missed Detects per Burst Threshold
value stored in address 2F
H
. Under normal operating con-
ditions, the Z87200 will automatically return to acquisition
mode when the number of symbols processed in the burst
is equal to the value of the data stored in address 2E
H
and
30
H
. To permit the processing of longer bursts or continu-
ous data, this function can be disabled by setting bit 6 of
address 30
H
high.
Differential Demodulator
Both DPSK demodulation and carrier discrimination are
supported in the Z87200 receiver by the calculation of
“Dot” and “Cross” products using the despread I and Q
channel information generated by the PN Matched Filter
for the current and previous symbols. A block diagram of
the DPSK Demodulator’s I and Q channel processing is
shown in Let I
k
and Q
k
represent the I and Q channel out-
puts, respectively, for the k
th
symbol. The Dot and Cross
products can then be defined as:
Dot(k) = I
k
I
k-1
+ Q
k
Q
k-1
; and,
Cross(k) = Q
k
I
k-1
- I
k
Q
k-1
.
Examination of these products in the complex plane re-
veals that the Dot and Cross products are the real and
imaginary results, respectively, of complex multiplication
of the current and previous symbols. The Dot product
alone thus allows determination of the phase shift between
successive BPSK symbols, while the Dot and Cross prod-
ucts together allow determination of the integer number of
π/2 phase shifts between successive QPSK symbols. Dif-
ferential encoding of the source data implies that an abso-
lute phase reference is not required, and thus knowledge
of the phase shift between successive symbols derived
from the Dot and Cross products unambiguously permits
correct demodulation.
Implementation of this approach is simplified if the polari-
ties (the signs) alone of the Dot and Cross products pro-
vide the information required to make the correct symbol
decision. For BPSK and π/4 QPSK signals, no modifica-
tions are needed: in BPSK, the sign of the Dot product fully
captures the signal constellation, while, in π/4 QPSK, the
signal constellation intrinsically includes the phase rotation
needed to align the decision boundaries with the four pos-
sible combinations of the Dot and Cross product polarities.
For QPSK signals, a fixed phase rotation of π/4 (45°) is in-
troduced in the DPSK Demodulator to the previous symbol
to simplify the decision algorithm. Rotation of the previous
symbol is controlled by the settings of bits 0 and 1 of ad-
dress 33
H
, allowing the previous symbol to be rotated by
0° or ±45°. As noted, for BPSK or π/4 QPSK signals, a ro-
tation of 0° should be programmed, but, for QPSK signals,

Z8720045FSC

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Manufacturer:
ZiLOG
Description:
RF Transceiver SS MODEM
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