Z87200
Zilog Spread-Spectrum Transceiver
4-9
A.C. CHARACTERISTICS - TRANSMITTER
Operating Conditions: V
DD
= 5.0V ±5%, V
SS
= 0V
T
A
0°C to +70°C
Symbol Parameter Min Max Units Conditions
f
TXIFCLK
TXIFCLK Frequency 45.056
20.0
MHz
MHz
Z0200045FSC
Z0200020FSC or if
TXIFOUT is used
t
CH
TXIFCLK Pulse width, High 10 ns
t
CL
TXIFCLK Pulse width, Low 10 ns
t
SU
TXIN to TXIFCLK setup 3 ns
t
HD
TXIN to TXIFCLK hold 5 ns
t
CT
TXIFCLK to TXBITPLS,
TXTRKPLS, XACQPLS,
TXIOUT or TXQOUT delay
35 ns
Notes:
1. The number of TXIFCLK cycles per cycle of TXCHPPLS is determined by the data stored in bits 5-0 of address 41
H
. It is shown
as 2 in Figure 8 but can be set from 2 to 64.
2. The width of the TXBITPLS, TXTRKPLS and TXACQPLS signal pulses is equal to the period of TXCHPPLS; that is, equal to
the PN chip period.
3. In QPSK mode, the TXBITPLS signal pulses high twice during each symbol period, once during the center chip and once
during the last chip. If the number of chips per symbol is even, the number of chip periods between the TXBITPLS pulse at
the end of the previous symbol and the one in the center of the symbol will be one more than the number of chip periods
between the TXBITPLS pulse in the center of the symbol and the one at the end. The falling edge of the second pulse corre-
sponds to the end of the symbol period.
4. The TXTRKPLS signal pulses high once each symbol period, during the last chip period of that symbol. The falling edge cor-
responds to the end of the symbol period.
5. The TXACQPLS signal pulses high once each burst, transmission, during the last chip of the Acquisition/Preamble symbol.
The falling edge corresponds to the end of this symbol period.
