Z8720045FSG Datasheet Z8720045FSC, Z8720045FSG, Z8720020FSC | P49-P51

Z87200

Zilog Spread-Spectrum Transceiver

4-47

Differential Demodulation

As noted in the preceding text, computation of the “Dot”

and “Cross” products is fundamental to operation of the

DPSK Demodulator and Frequency Discriminator. Let I

and Q

represent the I and Q channel inputs, respectively,

for the k

symbol after downconversion and despreading.

The Dot and Cross products can then be defined as:

Dot(k) = I

k-1

+ Q

k-1

; and,

Cross(k) = Q

k-1

- I

k-1

In the complex domain, these products can be seen to

have been defined to form the complex conjugate product

between two input samples, one symbol apart. Let the k

input sample, sin(k), be defined as:

(k) = I(k) + j Q(k),

where I(k) and Q(k) are the 8-bit peak power PN Matched

Filter I and Q channel outputs directed to the DPSK De-

modulator. In polar form, s

(k) may be conveniently de-

fined as:

(k) = A(k)e

jØ(k)

with

A(k)

Ø(k) = arctan

Simple substitution then shows that the complex conjugate

product between consecutive symbols (with an arbitrary

phase shift introduced to the previous symbol value) may

be expressed as:

out

(k)= s

(k) [s

(k–1) . ω

fixed

]

= Dot(k) + j Cross(k)

where

fixed

= arbitrary fixed phase rotation;

Dot(k)= Re[s

out

(k)]; and,

Cross(k)= Im[s

out

(k)]

The fixed phase rotation ω

fixed

has been introduced to later

simplify the decision criteria. The ability to express real and

imaginary parts of the complex conjugate product between

consecutive symbols with the Dot and Cross products is

the key to their use in DPSK demodulation.

DBPSK Demodulation

In DPSK, the phase difference between successive sam-

ples is due to the data modulation phase differences,

∆Ømod, plus any induced phase rotation between sym-

bols, ∆Ørot, resulting from, for example, a frequency offset

between the received signal’s I.F. and that provided by the

Downconverter. For DBPSK, the data modulation differ-

ences ∆Ømod can take only the values of 0° or 180°. Ex-

pressing the complex phase difference [Ø(k)-Ø(k-1)] in

terms of these components, the decision can be seen to be

based on:

Sout

(k)

=A(k) A(k-1) e

jØ(k)*

-jØ(k-1)

= A(k)

A(k1)

j[∆Ø

mod

(k)+∆Ø

rot

(k)]

For DBPSK, only the real part of sout(k), Dot(k), is needed

to determine the modulated phase transition:

Dot(k)= A(k)

A(k-1)

cos(∆Ø

mod

(k)+∆Ørot(k))

= ±A(k)

A(k-1)

cos(∆Ø

rot

(k))

where the sign is determined by the transmitted data since

cos[∆Ø

mod

(k)] = ±1

As a result,

Dot(k)≈ ±A

(k)

if the amplitude of the signal is constant for consecutive

symbols and if the phase rotation ∆Ø

rot

(k) between sym-

bols is small. The Z87200 DPSK Demodulator can thus

use the sign of the Dot product in order to make DBPSK

symbol decisions without the introduction of any fixed

phase rotation.

PS010202-0601

Z87200

Spread-Spectrum Transceiver Zilog

4-48

THEORY OF OPERATION (Continued)

DQPSK Demodulation

For DQPSK modulation, the possible phase shifts be-

tween successive symbols due to the modulation are 0°,

90°, 180°, and 270°. Here, introduction of a phase shift

(ω

fixed

) of ±45° to the previous symbol in the calculation of

the Dot and Cross products is desired in order shift the

possible phase differences to 45°, 135°, 225°, or 315° so

that the DQPSK decision boundaries coincide with the

signs of the Dot and Cross products. In the Z87200 DPSK

demodulator, phase rotation is accomplished in the signal

rotation block by the following transformation of the I and

Q channel values:

rot

(k)=[ I(k) - Q(k)]/2 for 45° rotation

rot

(k)=[ I(k) + Q(k)]/2 for –45° rotation

rot

(k)=[ I(k) + Q(k)]/2 for 45° rotation

rot

(k)=-[ I(k) + Q(k)]/2 for –45° rotation

The divide-by-2 is part of the signal rotation function. This

transformation is equivalent to multiplying by (1 ± j)/2 or

(1/√2)e

jØ(fixed)

where Ø

fixed

is ±45°. In this case, s

out

(k) be-

comes:

out

(k)=A(k).A(k-1)*e

jØ(k)*

–jØ(k-1)*

[ω

fixed

=A(k).A(k-1)*e

j[∆Ø

mod

(k)+∆Ø

rot

(k)]*

(1/√2)ej

Ø(fixed)

so that

Dot(k)≈(1/√2)A(k)*A(k-1)*cos(∆Ø

mod

(k) - Ø

fixed

)

Cross(k)≈(1/√2)A(k)*A(k-1)*sin(∆Ø

mod

(k) - Ø

fixed

)

where the phase rotation ∆Ø

rot

(k) due to the frequency off-

set between symbols has been assumed negligible.

A summary of the Dot(k) and Cross(k) products for the

possible values of ∆Ø

mod

(k) and Ø

fixed

is shown below, il-

lustrating how the sign of the Dot and Cross products allow

the symbol decision to be made:

π/4 QPSK Demodulation

The Z87200 DPSK Demodulator decision logic is de-

signed so that correct DQPSK decisions are made with a

signal rotation of Ø

fixed

= –45°. For π/4 QPSK modulation,

however, the modulator itself inserts 45° between consec-

utive symbols, and the possible phase shifts between suc-

cessive symbols due to modulation are 45°, 135°, 225°,

and 315°. As a result, the DPSK Demodulator should be

configured for π/4 QPSK with Ø

fixed

=0°.

DQPSK Phasing and I/Q Channel Reversal

The Z87200 uses Differential BPSK and QPSK modulation

and demodulation, meaning that the data is modulated on

the carrier as phase changes. At the demodulator, the data

is recovered by monitoring the phase change over a sym-

bol period.

The Z87200 provides configuration control to specifically

address DPSK phasing and I/Q channel reversal: the Sig-

nal Rotation control register, bits 0 and 1 of address 33

and the Reverse I and Q control register, bit 0 of address

. The first register causes an insertion of ±45° in phase

between consecutive symbols at the receiver, while the

second register switches the I and Q channels presented

to the DPSK demodulator. As discussed in the Z87200 ap-

pendix, the introduction of a phase shift between consec-

utive symbols changes the mapping of the input data with

respect to the decision boundaries defined by the "Cross"

and "Dot" product axes.

Assuming that the transmitted DQPSK modulation phas-

ing is differentially encoded as defined in Table 3, the

phase shift between consecutive symbols should always

be set to –45°; that is, bits 1 and 0 of address 33

should

be set to 11. Similarly, when the transmission path from

modulator to demodulator does not introduce a frequency

(or phase direction) reversal, the "reverse I and Q" control

function should be disabled; that is, bit 0 of address 36H

should be set to 0. Note that, in the case of DBPSK, the

phase increments are either 0 or 180° and frequency re-

versal has no impact.

If frequency reversal does take place, however, correct

DQPSK demodulation can be achieved by enabling I and

Q reversal; that is, the entry into bit 0 of address 36

should be set to 1. Frequency reversal may occur in the up

or down conversion process, depending on which mixing

product is selected for further processing. No reversal oc-

curs when the following conditions exist: when the mixing

()

Q(k)

I(k)

(K)+Q

(k)

ﬁxed

= -45° Ø

ﬁxed

= +45°

∆Ø

mod

(k)

Dot(k)

Cross

(k)

∆Ø

mod

(k) Dot(k)

Cross

(k)

0°

–A

90°

–A

90°

180°

–A

180°

–A

270°

–A

270°

–A

PS010202-0601

Z87200

Zilog Spread-Spectrum Transceiver

4-49

at the transmitter is performed by processing the sum fre-

quency of the local oscillator and the modulator; when the

mixing at the receiver is performed by subtracting the local

oscillator from the incoming signal; and when the in-phase

and quadrature inputs into the I and Q analog-to-digital

converters are correctly connected such that the in-phase

component leads the quadrature component by 90°. Un-

der these conditions, bit 0 of address 36

should be set to

0; otherwise, the I and Q channels may need to be re-

versed at the DPSK demodulator (by setting bit 0 of ad-

dress 36

to 1) in order to achieve proper demodulation.

Frequency Error Signal Generation

The frequency discriminator function or error signal is gen-

erated based on the Dot and Cross products. The objec-

tive is an error signal that is proportional to the sine of the

phase difference between the present and prior symbol af-

ter correcting for the estimated phase increments due to

data modulation. In the Z87200 Frequency Discriminator,

the frequency error is calculated through a decision-direct-

ed cross-product algorithm and is then used with the Loop

Filter to correct the NCO frequency. Assuming an input

sin(k), where:

(k) = I(k) + j Q(k),

the algorithm calculates the frequency discriminator func-

tion for DBPSK, s

AFC/BPSK

(k), as:

AFC/BPSK

(k)=SIGN[Dot(k)]*Cross(k)

=SIGN[Dot(k)]*A(k)*A(k-1)*sin(Ø(k)-Ø(k-1))

=SIGN[Dot(k)]*A(k)*A(k-1)*sin(∆Ømod(k) + ∆Ørot(k))

≈SIGN[Dot(k)]*A2(k)*cos[∆Ømod(k)]*sin[∆Ørot(k)]

≈A2(k)*sin[∆Ørot(k)]*

The final result assumes that the amplitude of the signal is

constant over consecutive symbols and shows that the

discriminator function is directly related to the change in

phase between successive symbols. Since the interval be-

tween successive symbols is fixed, the discriminator func-

tion can be interpreted as a frequency error signal.

For DQPSK signals, the Z87200 computes the discrimina-

tor function S

AFC/QPSK

(k) as:

AFC/QPSK(

k)=SIGN[Dot(k)] Cross(k) - SIGN[Cross(k)]

Dot(k),

where the above expression can be reduced to the same

as for DBPSK,

AFC/QPSK

(k)≈A2(k)*sin(∆Ørot(k)).

BPSK/QPSK Modulation

The Z87200 incorporates a Direct Digital Synthesizer

(DDS) to implement its on-chip BPSK/QPSK modulator. In

the Z87200 design, the NCO and thus the sampling clock

for the modulator is driven by fRXIFCLK; for this reason,

both TXIFCLK and RXIFCLK must be common if the on-

chip BPSK/QPSK modulator is to be used. The

BPSK/QPSK modulator can then be used to generate the

transmit output signal at a programmable IF frequency,

thereby eliminating the need for an external modulator.

Because it is a sampled data system like the Downconvert-

er of the Z87200, however, care must be taken to ensure

that the results of aliasing do not adversely affect the out-

put transmit signal.

PS010202-0601

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Z8720045FSG

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Z8720045FSG

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