Z8720045FSG Datasheet Z8720045FSC, Z8720045FSG, Z8720020FSC | P31-P33

Z87200

Zilog Spread-Spectrum Transceiver

4-29

Bits 7-4 — Integrate and Dump Filter Viewport Control

The Z87200 incorporates viewport (data selector) circuitry

to select any three consecutive bits from the 14-bit output

of the Integrate and Dump (I & D) Filters in the Downcon-

verter block as the 3-bit inputs to the dual-channel PN

Matched Filter. The signal levels of the Integrate and

Dump Filter I and Q outputs reflect the input signal levels

and the number of samples integrated before the filter con-

tents are “dumped,” where the number of samples is deter-

mined by the baseband sampling rate (nominally, twice the

PN chip rate) and the I.F. sampling rate (RXIFCLK). Set-

ting the viewport thus effectively normalizes the I & D Filter

outputs before further processing. The unsigned value, n,

of bits 7-4 of address 01

determines the 3-bit inputs to the

PN Matched Filter as the14-bit I & D Filter outputs divided

by 2

. Equivalently, bits 7-4 control the viewport of the In-

tegrate and Dump Filter outputs as shown in Note that

viewport control affects both I and Q channels of the Inte-

grate and Dump Filters.

Saturation protection is implemented for those cases when

the Integrate and Dump Filter output signal level overflows

the scaled range selected for the PN Matched Filter. When

the scaled value range is exceeded, the saturation protec-

tion limits the output word to the maximum or minimum val-

ue of the range according to whether the positive or nega-

tive boundary was exceeded.

Address 02

Bits 5-0 — Receiver Baseband Sampling (Dump) Rate

Control

The baseband sampling rate should be set to twice the

nominal PN chip rate of the received signal and must be

less than or equal to half the rate of RXIFCLK. When bit 0

of address 01

is set low, the baseband sampling clock for

the Integrate and Dump Filter and all subsequent receiver

circuitry is referenced to RXIFCLK and generated internal-

ly. The receiver baseband sampling rate is then set to the

frequency of RXIFCLK/(n+1), where n is the value stored

in bits 5-0 and must range from 1 to 63. This feature is use-

ful in cases where a specific sample rate is required that is

an integer sub-multiple of f

RXIFCLK

. In cases where a sam-

ple rate is required that is not an integer sub-multiple of

RXIFCLK

, an external baseband sampling rate can be pro-

vided by the RXMSMPL input.

Addresses 03

through 06

NCO Frequency Control Word

The Z87200’s internal NCO is driven by a frequency con-

trol word that is the sum of the frequency discriminator er-

ror value (generated in the demodulator) and the 32-bit fre-

quency control word (FCW) stored in this location. The four

8-bit registers at addresses 03

to 06

are used to store

the 32-bit frequency control word as shown in The LSB of

each byte is stored in bit 0 of each register.

The NCO frequency is then set by the FCW according to

the following formula:

In order to avoid in-band aliasing, f

NCO

must not exceed

50% of f

RXIFCLK

; normally, the FCW should be set so that

NCO

does not exceed ~35% of f

RXIFCLK

. While this limita-

tion may seem to restrict use of the NCO, higher I.F. trans-

mit or receive frequencies can generally be achieved by

using aliases resulting from digital sampling. The signal

bandwidth with respect to f

RXIFCLK

, the modulation type,

and the use of Direct I.F. or Quadrature Sampling Mode

also restrict the choice of NCO frequency, Theory of Oper-

ation.

PN Matched Filter Registers

Despreading of the received signal is accomplished in the

Z87200 with a dual (I and Q channel) PN Matched Filter.

Furthermore, the Z87200 is designed for burst signal oper-

ation, where each data burst begins with an Acquisi-

tion/Preamble symbol and is then followed by the actual in-

formation data symbols. Two separate and independent

PN codes can be employed, one for the Acquisition/Pre-

amble symbol, the other for the information symbols. Ac-

cordingly, the PN Matched Filter is supported by two PN

code registers to independently allow the programming of

two distinct codes up to 64 chips in length. The PN codes

are represented as a sequence of ternary-valued tap coef-

Table 6. Integrate & Dump Filter Viewport Control

Bits 7-4 I & D Bits Output to Matched Filter

2-0

3-1

4-2

5-3

• • • • • •

12-10

13-11

Table 7. Integrate & Dump Filter Viewport Control

ADDR06H ADDR 05H ADDR04H ADDR03H

Bits 31-24 Bits 23-16 Bits 15-8 Bits 7-0

RXIFCLK

x FCW

NCO

= __________

PS010202-0601

Z87200

Spread-Spectrum Transceiver Zilog

4-30

CONTROL REGISTERS (Continued)

ficients, each requiring 2 bits of storage according to the

mapping shown in Table 8.

As a convention, Tap 0 is the first tap as the received sig-

nal enters the PN Matched Filter, and Tap 63 is the last. All

active taps of the PN Matched Filter, from Tap 0 up to Tap

(N-1), where N is the length of the PN code, should be pro-

grammed with tap coefficient values of +1 or -1 according

to the PN code sequence. Setting the end coefficients of

the PN Matched Filter registers to zero values permits the

effective length of the filter to be made shorter than 64

taps.

Addresses 07

through 16

Matched Filter Acquisition/Preamble Symbol

Coefficients

Addresses 07

to 16

contain the 64 2-bit Acquisition/Pre-

amble PN code coefficient values. The 128 bits of informa-

tion are stored in 16 8-bit registers at addresses 07

to 16

as shown in Table 8.

Addresses 17

through 26

Matched Filter Data Symbol Coefficients

Addresses 17

to 26

contain the 64 2-bit Data Symbol

PN code coefficient values. The 128 bits of information are

stored in 16 8-bit registers at addresses 17

to 26

shown in The contents of addresses 17

to 26

are inde-

pendent of and not affected by the contents of addresses

to 16

Address 27

Bit 0 — Front End Processor Disable

The Front End Processor (FEP) averages the two base-

band samples per chip by adding consecutive pairs of

samples. The function may be disabled for test purposes

by using this bit: when set low, the FEP is enabled and in

its normal mode of operation; when set high, the FEP is

disabled.

Power Estimator Registers

Address 28

Bits 1-0 — Matched Filter Viewport Control

The Z87200 incorporates viewport (data selector) circuitry

to select any eight consecutive bits from the 10-bit outputs

of the PN Matched Filter as the 8-bit inputs to the Power

Estimator and DPSK Demodulator blocks. The Symbol

Tracking Processor, however, operates on the full 10-bit

PN Matched Filter outputs before the viewport is applied.

The signal levels of the PN Matched Filter output reflect

the number of chips per symbol and the signal-to-noise ra-

tio of the signal. Setting the viewport thus effectively nor-

malizes the PN Matched Filter outputs prior to further pro-

cessing. The unsigned value, n, of bits 1-0 of address 28

determines the 8-bit input to the Power Estimator and

DPSK Demodulator blocks as the 10-bit PN Matched Filter

output divided by 2

. Equivalently, bits 1-0 control the

viewport of the PN Matched Filter output as shown in Note

Table 8. PN Matched Filter Tap Values

Tap Bits 1,0 Tap Coeff

X0 0

01 +1

11 -1

Table 9. Acquisition/Preamble Coefﬁcient Storage

Address 16