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LTC2420CS8#TRPBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36
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LTC2420
APPLICATIO S I FOR ATIO
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The LTC2420 is pin compatible with the LTC2400. The two
devices are designed to allow the user to incorporate
either device in the same design with no modifications.
While the LTC2420 output word length is 24 bits (as
opposed to the 32-bit output of the LTC2400), its output
clock timing can be identical to the LTC2400. As shown in
Figure 1, the LTC2420 data output is concluded on the
falling edge of the 24th serial clock (SCK). In order to
maintain drop-in compatibility with the LTC2400, it is
possible to clock the LTC2420 with an additional 8 serial
clock pulses. This results in 8 additional output bits which
are always logic HIGH.
Converter Operation Cycle
The LTC2420 is a low power, delta-sigma analog-to-
digital converter with an easy to use 3-wire serial interface.
Its operation is simple and made up of three states. The
converter operating cycle begins with the conversion,
followed by a low power sleep state and concluded with
the data output (see Figure 2). The 3-wire interface con-
sists of serial data output (SDO), a serial clock (SCK) and
a chip select (CS).
Initially, the LTC2420 performs a conversion. Once the
conversion is complete, the device enters the sleep state.
While in this sleep state, power consumption is reduced by
an order of magnitude. The part remains in the sleep state
as long as CS is logic HIGH. The conversion result is held
indefinitely in a static shift register while the converter is
in the sleep state.
Once CS is pulled LOW, the device begins outputting the
conversion result. There is no latency in the conversion
result. The data output corresponds to the conversion just
performed. This result is shifted out on the serial data out
pin (SDO) under the control of the serial clock (SCK). Data
is updated on the falling edge of SCK allowing the user to
reliably latch data on the rising edge of SCK, see Figure 4.
The data output state is concluded once 24 bits are read
out of the ADC or when CS is brought HIGH. The device
automatically initiates a new conversion cycle and the
cycle repeats.
Through timing control of the CS and SCK pins, the
LTC2420 offers several flexible modes of operation
(internal or external SCK and free-running conversion
modes). These various modes do not require
program
ming configuration registers; moreover, they do
Figure 1. LTC2420 Compatible Timing with the LTC2400
CS
SCK
SDO
CONVERSION SLEEP
8 8 8 8 (OPTIONAL)
EOC = 1
EOC = 1
LAST 8 BITS ALWAYS 1
EOC = 0
DATA OUT
4 STATUS BITS 20 DATA BITS
DATA OUTPUT
2420 F01
CONVERSION
CONVERT
SLEEP
DATA OUTPUT
2420 F02
0
1
CS AND
SCK
Figure 2. LTC2420 State Transition Diagram
11
LTC2420
not disturb the cyclic operation described above. These
modes of operation are described in detail in the Serial
Interface Timing Modes section.
Conversion Clock
A major advantage delta-sigma converters offer over
conventional type converters is an on-chip digital filter
(commonly known as Sinc or Comb filter). For high
resolution, low frequency applications, this filter is typi-
cally designed to reject line frequencies of 50Hz or 60Hz
plus their harmonics. In order to reject these frequencies
in excess of 110dB, a highly accurate conversion clock is
required. The LTC2420 incorporates an on-chip highly
accurate oscillator. This eliminates the need for external
frequency setting components such as crystals or oscilla-
tors. Clocked by the on-chip oscillator, the LTC2420
rejects line frequencies (50Hz or 60Hz ±2%) a minimum
of 110dB.
Ease of Use
The LTC2420 data output has no latency, filter settling or
redundant data associated with the conversion cycle.
There is a one-to-one correspondence between the
conversion and the output data. Therefore, multiplexing
an analog input voltage is easy.
The LTC2420 performs offset and full-scale calibrations
every conversion cycle. This calibration is transparent to
the user and has no effect on the cyclic operation de-
scribed above. The advantage of continuous calibration is
extreme stability of offset and full-scale readings with re-
spect to time, supply voltage change and temperature drift.
Power-Up Sequence
The LTC2420 automatically enters an internal reset state
when the power supply voltage V
CC
drops below approxi-
mately 2.2V. This feature guarantees the integrity of the
conversion result and of the serial interface mode selec-
tion which is performed at the initial power-up. (See the
2-wire I/O sections in the Serial Interface Timing Modes
section.)
When the V
CC
voltage rises above this critical threshold,
the converter creates an internal power-on-reset (POR)
signal with duration of approximately 0.5ms. The POR
signal clears all internal registers. Following the POR
signal, the LTC2420 starts a normal conversion cycle and
follows the normal succession of states described above.
The first conversion result following POR is accurate
within the specifications of the device.
Reference Voltage Range
The LTC2420 can accept a reference voltage from 0V to
V
CC
. The converter output noise is determined by the
thermal noise of the front-end circuits, and as such, its
value in microvolts is nearly constant with reference
voltage. A decrease in reference voltage will not signifi-
cantly improve the converter’s effective resolution. On the
other hand, a reduced reference voltage will improve the
overall converter INL performance. The recommended
range for the LTC2420 voltage reference is 100mV to V
CC
.
Input Voltage Range
The converter is able to accommodate system level offset
and gain errors as well as system level overrange situa-
tions due to its extended input range, see Figure 3. The
LTC2420 converts input signals within the extended input
range of –0.125 • V
REF
to 1.125 • V
REF
.
For large values of V
REF
, this range is limited by the
absolute maximum voltage range of – 0.3V to (V
CC
+ 0.3V).
Beyond this range, the input ESD protection devices begin
to turn on and the errors due to the input leakage current
increase rapidly.
Input signals applied to V
IN
may extend below ground by
–300mV and above V
CC
by 300mV. In order to limit any
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2420 F03
V
CC
+ 0.3V
9/8V
REF
V
REF
1/2V
REF
–0.3V
–1/8V
REF
0
NORMAL
INPUT
RANGE
EXTENDED
INPUT
RANGE
ABSOLUTE
MAXIMUM
INPUT
RANGE
Figure 3. LTC2420 Input Range
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LTC2420
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fault current, a resistor of up to 25k may be added in series
with the V
IN
pin without affecting the performance of the
device. In the physical layout, it is important to maintain
the parasitic capacitance of the connection between this
series resistance and the V
IN
pin as low as possible;
therefore, the resistor should be located as close as
practical to the V
IN
pin. The effect of the series resistance
on the converter accuracy can be evaluated from the
curves presented in the Analog Input/Reference Current
section. In addition, a series resistor will introduce a
temperature dependent offset error due to the input leak-
age current. A 1nA input leakage current will develop a
1ppm offset error on a 5k resistor if V
REF
= 5V. This error
has a very strong temperature dependency.
Output Data Format
The LTC2420 serial output data stream is 24 bits long. The
first 4 bits represent status information indicating the
sign, input range and conversion state. The next 20 bits are
the conversion result, MSB first.
Bit 23 (first output bit) is the end of conversion (EOC)
indicator. This bit is available at the SDO pin during the
conversion and sleep states whenever the CS pin is LOW.
This bit is HIGH during the conversion and goes LOW
when the conversion is complete.
Bit 22 (second output bit) is a dummy bit (DMY) and is
always LOW.
Bit 21 (third output bit) is the conversion result sign indi-
cator (SIG). If V
IN
is >0, this bit is HIGH. If V
IN
is <0, this
bit is LOW. The sign bit changes state during the zero code.
Bit 20 (fourth output bit) is the extended input range (EXR)
indicator. If the input is within the normal input range
0␣ ≤␣V
IN
≤ V
REF
, this bit is LOW. If the input is outside the
normal input range, V
IN
> V
REF
or V
IN
< 0, this bit is HIGH.
The function of these bits is summarized in Table 1.
Table 1. LTC2420 Status Bits
Bit 23 Bit 22 Bit 21 Bit 20
Input Range EOC DMY SIG EXR
V
IN
> V
REF
0 011
0 < V
IN
≤ V
REF
0 010
V
IN
= 0
+
/0
–
0 0 1/0 0
V
IN
< 0 0 001
Bit 19 (fifth output bit) is the most significant bit (MSB).
Bits 19-0 are the 20-bit conversion result MSB first.
Bit 0 is the least significant bit (LSB).
Data is shifted out of the SDO pin under control of the serial
clock (SCK), see Figure 4. Whenever CS is HIGH, SDO
remains high impedance and any SCK clock pulses are
ignored by the internal data out shift register.
In order to shift the conversion result out of the device, CS
must first be driven LOW. EOC is seen at the SDO pin of the
device once CS is pulled LOW. EOC changes real time from
HIGH to LOW at the completion of a conversion. This
signal may be used as an interrupt for an external micro-
controller. Bit 23 (EOC) can be captured on the first rising
edge of SCK. Bit 22 is shifted out of the device on the first
falling edge of SCK. The final data bit (Bit 0) is shifted out
on the falling edge of the 23rd SCK and may be latched on
Figure 4. Output Data Timing
MSBEXTSIG“0”
12345 192024
BIT 0BIT 19 BIT 4
LSB
20
BIT 20BIT 21BIT 22
SDO
SCK
CS
EOC
BIT 23
SLEEP DATA OUTPUT CONVERSION
2420 F04
Hi-Z
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LTC2420CS8#TRPBF

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Buy LTC2420CS8#TRPBF
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 20-B Pwr No Lat Delta-Sigma ADC in SO-
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