22
LTC2420
APPLICATIO S I FOR ATIO
WUU
U
The internal serial clock mode is selected every time the
voltage on the CS pin crosses an internal threshold volt-
age. An internal weak pull-up at the SCK pin is active while
CS is discharging; therefore, the internal serial clock
timing mode is automatically selected if SCK is floating. It
is important to ensure there are no external drivers pulling
SCK LOW while CS is discharging.
DIGITAL SIGNAL LEVELS
The LTC2420’s digital interface is easy to use. Its digital
inputs (F
O
, CS and SCK in External SCK mode of operation)
accept standard TTL/CMOS logic levels and the internal
hysteresis receivers can tolerate edge rates as slow as
100µs. However, some considerations are required to take
advantage of exceptional accuracy and low supply current.
CAPACITANCE ON CS (pF)
0
SAMPLE RATE (Hz)
3
4
5
1000
100000
2420 F14
2
1
0
10 100 10000
6
7
8
V
CC
= 5V
V
CC
= 3V
Figure 14. CS Capacitance vs Output Rate
CAPACITANCE ON CS (pF)
1
0
SUPPLY CURRENT (µA
RMS
)
50
100
150
200
250
300
10 100 1000 10000
2420 F15
100000
V
CC
= 5V
V
CC
= 3V
Figure 15. CS Capacitance vs Supply Current
The digital output signals (SDO and SCK in Internal SCK
mode of operation) are less of a concern because they are
not generally active during the conversion state.
In order to preserve the LTC2420’s accuracy, it is very
important to minimize the ground path impedance which
may appear in series with the input and/or reference signal
and to reduce the current which may flow through this path.
The GND pin should be connected to a low resistance
ground plane through a minimum length trace. The use of
multiple via holes is recommended to further reduce the
connection resistance. The LTC2420’s power supply cur-
rent flowing through the 0.01Ω resistance of the common
ground pin will develop a 2.5µV offset signal. For a refer-
ence voltage V
REF
= 2.5V, this represents a 1ppm offset
error.
In an alternative configuration, the GND pin of the converter
can be the single-point-ground in a single point grounding
system. The input signal ground, the reference signal
ground, the digital drivers ground (usually the digital
ground) and the power supply ground (the analog ground)
should be connected in a star configuration with the com-
mon point located as close to the GND pin as possible.
The power supply current during the conversion state
should be kept to a minimum. This is achieved by restrict-
ing the number of digital signal transitions occurring
during this period.
While a digital input signal is in the range 0.5V to
(V
CC
␣ –␣ 0.5V), the CMOS input receiver draws additional
current from the power supply. It should be noted that,
when any one of the digital input signals (F
O
, CS and SCK
in External SCK mode of operation) is within this range, the
LTC2420 power supply current may increase even if the
signal in question is at a valid logic level. For micropower
operation and in order to minimize the potential errors due
to additional ground pin current, it is recommended to
drive all digital input signals to full CMOS levels
[V
IL
< 0.4V and V
OH
> (V
CC
– 0.4V)].
Severe ground pin current disturbances can also occur
due to the undershoot of fast digital input signals. Under-
shoot and overshoot can occur because of the imped-
ance mismatch at the converter pin when the transition
time of an external control signal is less than twice the
