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ICS9LPRS464AGLF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23
13
ICS9LPRS464
System Clock Chip for ATI RS/RD600 series chipsets using AMD CPUss
IDT
TM
/ICS
TM
System Clock Chip for ATI RS/RD600 series chipsets using AMD CPUs
1377A—04/07/08
SRC Reference Clock
Common Recommendations for Differential Routing Dimension or Value Unit Figure
L1 length, Route as non-coupled 50 ohm trace. 0.5 max inch 2
L2 length, Route as non-coupled 50 ohm trace. N/A inch 2
L3 length, Route as non-coupled 50 ohm trace. N/A inch 2
Rs 33 ohm 2
Rt 49.9 ohm 2
Down Device Differential Routing Dimension or Value Unit Figure
L4 length, Route as coupled microstrip 100 ohm differential trace.
2 min to 16 max inch 2
L4 length, Route as coupled stripline 100 ohm differential trace.
1.8 min to 14.4 max inch 2
Differential Routing to PCI Express Connector Dimension or Value Unit Figure
L4 length, Route as coupled microstrip 100 ohm differential trace.
0.25 to 14 max inch 3
L4 length, Route as coupled stripline 100 ohm differential trace.
0.225 min to 12.6 max inch 3
Figure 2 Down device routing.
PCI Ex Board
Down Device
REF_CLK Input
L1
L4
L1’
L4’
Figure 2
Figure 3 PCI Express Connector Routing.
Low Power Output Buffer
w/integrated series resistor
PCI Ex
Add In Board
REF_CLK Input
L1
L4
L1’
L4’
Figure 3
Low Power Output Buffer
w/integrated series resistor
14
ICS9LPRS464
System Clock Chip for ATI RS/RD600 series chipsets using AMD CPUss
IDT
TM
/ICS
TM
System Clock Chip for ATI RS/RD600 series chipsets using AMD CPUs
1377A—04/07/08
General SMBus serial interface information for the ICS9LPRS464
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2
(H)
• ICS clock will
acknowledge
• Controller (host) sends the begining byte location = N
• ICS clock will
acknowledge
• Controller (host) sends the data byte count = X
• ICS clock will
acknowledge
• Controller (host) starts sending
Byte N through
Byte N + X -1
• ICS clock will
acknowledge
each byte
one at a time
• Controller (host) sends a Stop bit
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the write address D2
(H)
• ICS clock will
acknowledge
• Controller (host) sends the begining byte
location = N
• ICS clock will
acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address D3
(H)
• ICS clock will
acknowledge
• ICS clock will send the data byte count = X
• ICS clock sends
Byte N + X -1
• ICS clock sends
Byte 0 through byte X (if X
(H)
was written to byte 8)
.
• Controller (host) will need to acknowledge each byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
ICS (Slave/Receiver)
T
WR
ACK
ACK
ACK
ACK
ACK
P
stoP bit
X Byte
Index Block Write Operation
Slave Address D2
(H)
Beginning Byte = N
WRite
starT bit
Controller (Host)
Byte N + X - 1
Data Byte Count = X
Beginning Byte N
T starT bit
WR WRite
RT Repeat starT
RD ReaD
Beginning Byte N
Byte N + X - 1
N Not acknowledge
PstoP bit
Slave Address D3
(H)
Index Block Read Operation
Slave Address D2
(H)
Beginning Byte = N
ACK
ACK
Data Byte Count = X
ACK
ICS (Slave/Receiver)
Controller (Host)
X Byte
ACK
ACK
15
ICS9LPRS464
System Clock Chip for ATI RS/RD600 series chipsets using AMD CPUss
IDT
TM
/ICS
TM
System Clock Chip for ATI RS/RD600 series chipsets using AMD CPUs
1377A—04/07/08
SMBus Table: Spread Spectrum Enable and CPU Frequency Select Register
Byte 0 Pin # Name Control Function Type 0 1 PWD
Bit 7
- FS Source
Latched Input or SMBus
Frequency Select
RW
Latched
Inputs
SMBus 0
Bit 6
- ATIG SS_EN ATIG Spread Spectrum Enable RW Disable Enable 0
Bit 5
- SRC SS_EN SRC Spread Spectrum Enable RW Disable Enable 0
Bit 4
- CPU SS_EN CPU Spread Spectrum Enable RW Disable Enable 0
Bit 3
- CPU FS3 CPU Freq Select Bit 3 RW 0
Bit 2
- CPU FS2 CPU Freq Select Bit 2 RW Latch
Bit 1
- CPU FS1 CPU Freq Select Bit 1 RW Latch
Bit 0
- CPU FS0 CPU Freq Select Bit 0 RW Latch
Note: Each Spread Spectrum Enable bit is independent from the other.
Bit(6:4) must all set to "1" in order to enable spread for CPU, SRC and ATIG clocks.
SMBus Table: Output Control Register
Byte 1 Pin # Name Control Function Type 0 1 PWD
Bit 7
7 48MHz_1 48MHz_1 Output Enable RW Disable Enable 1
Bit 6
6 48MHz_0 48MHz_0 Output Enable RW Disable Enable 1
Bit 5
54 REF2 REF2 Output Enable RW Disable Enable 1
Bit 4
55 REF1 REF1 Output Enable RW Disable Enable 1
Bit 3
56 REF0 REF0 Output Enable RW Disable Enable 1
Bit 2
51 HTTCLK0 HTTCLK0 Output Enable RW Disable Enable 1
Bit 1
44,43 CPUCLK1 CPUCLK1 Output Enable RW Disable Enable 1
Bit 0
48,47 CPUCLK0 CPUCLK0 Output Enable RW Disable Enable 1
SMBus Table: ATIGCLK and CLKREQB# Output Control Register
Byte 2 Pin # Name Control Function Type 0 1 PWD
Bit 7
0
Bit 6
0
Bit 5
31,30 ATIGCLK1 ATIGCLK1 Output Enable RW Disable Enable 1
Bit 4
35,34 ATIGCLK0 ATIGCLK0 Output Enable RW Disable Enable 1
Bit 3
20,21 REQBSRC2 CLKREQB# Controls SRC2 RW
Does not
control
Controls 0
Bit 2
0
Bit 1
24,25 REQBSRC1 CLKREQB# Controls SRC1 RW
Does not
control
Controls 0
Bit 0
0
SMBus Table: SRCCLK Output Control Register
Byte 3 Pin # Name Control Function Type 0 1 PWD
Bit 7
12,13 SRCCLK5 RW Disable Enable 1
Bit 6
16,17 SRCCLK4 RW Disable Enable 1
Bit 5
18,19 SRCCLK3 RW Disable Enable 1
Bit 4
20,21 SRCCLK2 RW Disable Enable 1
Bit 3
Reserved - - - 1
Bit 2
24,25 SRCCLK1 RW Disable Enable 1
Bit 1
Reserved - - - 1
Bit 0
39,38 SRCCLK0 RW Disable Enable 1
See Table 1:
CPU Frequency Selection
Table
Master Output control. Enables
or disables output, regardless of
CLKREQ# inputs.
Reserved
Reserved
Reserved
Reserved
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23

ICS9LPRS464AGLF

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Buy ICS9LPRS464AGLF
Manufacturer:
Description:
IC CLOCK LP ATI RS/RD600 56TSSOP
Lifecycle:
New from this manufacturer.
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