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9LRS3165BKLF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28
IDT
®
64-pin CK505 Compatible Clock w/Fully Integrated Voltage Regulator + Integrated Series Resistor 1533B—01/06/15
9LRS3165B
64-pin CK505 Compatible Clock w/Fully Integrated Voltage Regulator + Integrated Series Resistor
16
Table 3: IO_Vout select table
B9b2 B9b1 B9b0 IO_Vout
000
0.3V
001
0.4V
010
0.5V
011
0.6V
100
0.7V
101
0.8V
110
0.9V
1 1 1 1.0V
Table 4: Device ID table
000 0
64 pin MLF
000 1
64 pin TSSOP
001 0 Reserved
001 1 Reserved
010 0 Reserved
010 1 Reserved
011 0 Reserved
011 1 Reserved
110 0 Reserved
110 1 Reserved
111 0 Reserved
111 1 Reserved
110 0 Reserved
110 1 Reserved
111 0 Reserved
111 1 Reserved
CommentB8b7 B8b6 B8b5 B8b4
IDT
®
64-pin CK505 Compatible Clock w/Fully Integrated Voltage Regulator + Integrated Series Resistor 1533B—01/06/15
9LRS3165B
64-pin CK505 Compatible Clock w/Fully Integrated Voltage Regulator + Integrated Series Resistor
17
PD# CPU_STOP# PCI_STOP# PEREQ#
SMBus
Register
OE
CPU0 CPU0# CPU1 CPU1# CPU2 CPU2#
1 1 1 X Enable
Running Running Running Running Running Running
0 X X X Enable
Low/20K Low Low/20K Low Low/20K Low
1 0 X X Enable
High Low High Low High Low
1 X X X Disable
Low/20K Low Low/20K Low Low/20K Low
Low/20K Low Running Running Low/20K Low
CPU Power Management Table
M1
PCIEX, LCD Power Management Table
PD# CPU_STOP# PCI_STOP# PEREQ#
SMBus
Register
OE
PCIeT PCIeC PCIeT PCIeC LCD LCD # LCD LCD # SATA SATA# SATA SATA#
1 X 1 0 Enable
Running Running Running Running Running Running Running Running Running Running Running Running
0 X X X Enable Low/20K Low Low/20K Low Low/20K Low Low/20K Low Low/20K Low Low/20K Low
1 X 0 0 Enable Running Running High Low Running Running High Low Running Running High Low
1 X X 1 Enable
Running Running Low/20K Low Running Running Running Running Running Running Running Running
1 X X X Disable Low/20K Low Low/20K Low Low/20K Low Low/20K Low Low/20K Low Low/20K Low
Low/20K Low Low/20K Low Low/20K Low Low/20K Low Low/20K Low Low/20K Low
Free-Run Stoppable
M1
Free-Run StoppableFree-Run Stoppable
DOT, SATA Power Management Table
PD# CPU_STOP# PCI_STOP# PEREQ#
SMBus
Register
OE
DOT DOT#
1 X 1 X Enable
Running Running
0 X X X Enable
Low/20K Low
1 X 0 X Enable
Running Running
1 X X X Enable
Running Running
1 X X X Disable
Low/20K Low
Low/20K Low
M1
PD# CPU_STOP# PCI_STOP# PEREQ#
SMBus
Register
OE
PCIF/PCI PCIF/PCI USB48 REF 27M SE
Free-Run Stoppable
1 X 1 X Enable
Running Running Running Running Running Running
0 X X X Enable
Low Low Low Low Low Low
1 X 0 X Enable
Running Low Running Running Running Running
1 X X X Disable
Low Low Low Low Low Low
Low Low Low Low Low Low
Singled-ended Power Management Table
M1
IDT
®
64-pin CK505 Compatible Clock w/Fully Integrated Voltage Regulator + Integrated Series Resistor 1533B—01/06/15
9LRS3165B
64-pin CK505 Compatible Clock w/Fully Integrated Voltage Regulator + Integrated Series Resistor
18
General SMBus serial interface information for the ICS9LRS3165B
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2
(H)
• ICS clock will
acknowledge
• Controller (host) sends the beginning byte location = N
• ICS clock will
acknowledge
• Controller (host) sends the data byte count = X
• ICS clock will
acknowledge
• Controller (host) starts sending
Byte N through
Byte N + X -1
• ICS clock will
acknowledge
each byte
one at a time
• Controller (host) sends a Stop bit
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the write address D2
(H)
• ICS clock will
acknowledge
• Controller (host) sends the begining byte
location = N
• ICS clock will
acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address D3
(H)
• ICS clock will
acknowledge
• ICS clock will send the data byte count = X
• ICS clock sends
Byte N + X -1
• ICS clock sends
Byte 0 through byte X (if X
(H)
was written to byte 8)
.
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
ICS (Slave/Receiver)
T
WR
ACK
ACK
ACK
ACK
ACK
P
stoP bit
X Byte
Index Block Write Operation
Slave Address D2
(H)
Beginning Byte = N
WRite
starT bit
Controller (Host)
Byte N + X - 1
Data Byte Count = X
Beginning Byte N
T starT bit
WR WRite
RT Repeat starT
RD ReaD
Beginning Byte N
Byte N + X - 1
N Not acknowledge
PstoP bit
Slave Address D3
(H)
Index Block Read Operation
Slave Address D2
(H)
Beginning Byte = N
ACK
ACK
Data Byte Count = X
ACK
ICS (Slave/Receiver)
Controller (Host)
X Byte
ACK
ACK
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28

9LRS3165BKLF

Mfr. #:
Buy 9LRS3165BKLF
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner PC MAIN CLOCK
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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