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9LRS3165BKLF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28
IDT
®
64-pin CK505 Compatible Clock w/Fully Integrated Voltage Regulator + Integrated Series Resistor 1533B—01/06/15
9LRS3165B
64-pin CK505 Compatible Clock w/Fully Integrated Voltage Regulator + Integrated Series Resistor
19
Byte 0 FS Readback & PLL Selection Register
Bit Name Description Type 0 1 Default
7FSLC
CPU Fre
q
. Sel. Bit
(
Most Si
g
nificant
)
R Latch
6FSLB
CPU Fre
q
. Sel. Bit
R Latch
5FSLA
CPU Fre
q
. Sel. Bit
(
Least Si
g
nificant
)
R Latch
4 iAMT_EN Set via SMBus or dynamically by CK505 if detects dynamic M1 R Legacy Mode iAMT Enabled
iAMT power on
status
3 Reserved
Reserved
RW 0
2 SRC_Main_SEL
Select source for SRC Main
RW
SRC Main = PLL5 SRC Main = PLL2
0
1 SATA_SEL
Select source for SATA clock
RW
SATA = SRC_Main SATA = PLL3
0
0 PD_Restore
1 = on Power Down de-assert return to last known state
0 = clear all SMBus configurations as if cold power-on and go to
latches open state
This bit is ignored and treated at '1' if device is in iAMT mode.
RW Configuration Not Saved Configuration Saved 1
Byte 1 PLL1 Quick Config Register
Note 1 : When 27_Select pin = 0, B1b7 PWD = 1; When 27_Select pin = 1, PWD = 0
Bit Name Description Type 0 1 Default
7 SRC0_SEL
Select SRC0 or DOT96
RW
SRC0 DOT96
Note 1
6 PLL5_SSC_SEL
Select 0.5% down or center SSC
RW
Down s
p
read Center s
p
read
0
5 PLL2_SSC SEL Select 0.5% center or down SSC RW
Down Center
0
4 PLL1_CF3
PLL1 Quick Confi
g
Bit 3
RW 0
3 PLL1_CF2
PLL1 Quick Confi
g
Bit 2
RW 0
2 PLL1_CF1
PLL1 Quick Confi
g
Bit 1
RW 1
1 PLL1_CF0
PLL1 Quick Confi
g
Bit 0
RW 0
0 PCI_SEL PCI_SEL RW PCI from PLL5 PCI from SRC_MAIN 1
Byte 2 Single Ended Output Enable Register
Bit Name Description Type 0 1 Default
7REF_OE
Out
p
ut enable for REF
RW
Out
p
ut Disabled Out
p
ut Enabled
1
6USB_OE
Out
p
ut enable for USB
RW
Out
p
ut Disabled Out
p
ut Enabled
1
5 PCIF5_OE
Out
p
ut enable for PCI5
RW
Out
p
ut Disabled Out
p
ut Enabled
1
4 PCI4_OE
Out
p
ut enable for PCI4
RW
Out
p
ut Disabled Out
p
ut Enabled
1
3 PCI3_OE
Out
p
ut enable for PCI3
RW
Out
p
ut Disabled Out
p
ut Enabled
1
2 PCI2_OE
Out
p
ut enable for PCI2
RW
Out
p
ut Disabled Out
p
ut Enabled
1
1 PCI1_OE
Out
p
ut enable for PCI1
RW
Out
p
ut Disabled Out
p
ut Enabled
1
0 PCI0_OE Output enable for PCI0 RW Output Disabled Output Enabled 1
Byte 3 SRC Output Enable Register
Bit Name Description Type 0 1 Default
7 SRC11_OE
Out
p
ut enable for SRC11
RW
Out
p
ut Disabled Out
p
ut Enabled
1
6 SRC10_OE
Out
p
ut enable for SRC10
RW
Out
p
ut Disabled Out
p
ut Enabled
1
5 SRC9_OE
Out
p
ut enable for SRC9
RW
Out
p
ut Disabled Out
p
ut Enabled
1
4 SRC8/ITP_OE
Out
p
ut enable for SRC8 or ITP
RW
Out
p
ut Disabled Out
p
ut Enabled
1
3 SRC7_OE
Out
p
ut enable for SRC7
RW
Out
p
ut Disabled Out
p
ut Enabled
1
2 SRC6_OE
Out
p
ut enable for SRC6
RW
Out
p
ut Disabled Out
p
ut Enabled
1
1 Reserved
Reserved
RW
--
1
0 SRC4_OE Output enable for SRC4 RW Output Disabled Output Enabled 1
Byte 4 SRC/CPU/DOT Output Enable & Spread Spectrum Disable Register
Bit Name Description Type 0 1 Default
7 SRC3_OE
Out
p
ut enable for SRC3
RW
Out
p
ut Disabled Out
p
ut Enabled
1
6 SATA/SRC2_OE
Out
p
ut enable for SATA/SRC2
RW
Out
p
ut Disabled Out
p
ut Enabled
1
5 SRC1_OE
Out
p
ut enable for SRC1
RW
Out
p
ut Disabled Out
p
ut Enabled
1
4 SRC0/DOT96_OE
Out
p
ut enable for SRC0/DOT96
RW
Out
p
ut Disabled Out
p
ut Enabled
1
3 CPU1_OE
Out
p
ut enable for CPU1
RW
Out
p
ut Disabled Out
p
ut Enabled
1
2 CPU0_OE
Out
p
ut enable for CPU0
RW
Out
p
ut Disabled Out
p
ut Enabled
1
1 PLL5_SSC_ON
Enable PLL5's s
p
read modulation
RW
S
p
read Disabled S
p
read Enabled
1
0 PLL2_SSC_ON Enable PLL2's spread modulation RW Spread Disabled Spread Enabled 1
Byte 5 Clock Request Enable/Configuration Register
Bit Name Description Type 0 1 Default
7 CR#_A_EN
Enable CR#_A
(
clk re
q)
for SRC0 or SRC2
RW Disable CR#_A Enable CR#_A 0
6 CR#_A_SEL
Sets CR#_A to control either SRC0 or SRC2
RW CR#_A -> SRC0 CR#_A -> SRC2 0
5 CR#_B_EN
Enable CR#_B
(
clk re
q)
for SRC1 or SRC4
RW Disable CR#_B Enable CR#_B 0
4 CR#_B_SEL
Sets CR#_B to control either SRC1 or SRC4
RW CR#_B -> SRC1 CR#_B -> SRC4 0
3 CR#_C_EN
Enable CR#_C
(
clk re
q)
for SRC0 or SRC2
RW Disable CR#_C Enable CR#_C 0
2 CR#_C_SEL
Sets CR#_C to control either SRC0 or SRC2
RW CR#_C -> SRC0 CR#_C -> SRC2 0
1 CR#_D_EN
Enable CR#_D
(
clk re
q)
for SRC1 or SRC4
RW Disable CR#_D Enable CR#_D 0
0 CR#_D_SEL Sets CR#_D to control either SRC1 or SRC4 RW CR#_D -> SRC1 CR#_D -> SRC4 0
See Table 1 : CPU Frequency Select Table
See Table 2: pin 27FIX/LCDT/SRCT_LR1/SE1,
27SS/LCDC/SRCC_LR1/SE2 Configuration
Only applies if Byte 0, bit 2 = 0.
IDT
®
64-pin CK505 Compatible Clock w/Fully Integrated Voltage Regulator + Integrated Series Resistor 1533B—01/06/15
9LRS3165B
64-pin CK505 Compatible Clock w/Fully Integrated Voltage Regulator + Integrated Series Resistor
20
Byte 6 Clock Request Enable/Configuration Register
Bit Name Description Type 0 1 Default
7 CR#_E_EN
Enable CR#_E
(
clk re
q)
for SRC6
RW Disable CR#_E Enable CR#_E 0
6 CR#_F_EN
Enable CR#_F
(
clk re
q)
for SRC8
RW Disable CR#_F Enable CR#_F 0
5 CR#_G_EN
Enable CR#_G
(
clk re
q)
for SRC9
RW Disable CR#_G Enable CR#_G 0
4 CR#_H_EN
Enable CR#_H
(
clk re
q)
for SRC10
RW Disable CR#_H Enable CR#_H 0
3
Reserved Reserved RW - -
0
2
Reserved Reserved RW - -
0
1 LCD/SRC1_STP_CRTL• If set, LCD_SS/SRC1 stops with PCI_STOP# RW Free Running
Stops with PCI_STOP#
assertion
0
0 SRC0_STP_CRTL If set, SRC0 stop with PCI_STOP# RW Free Running
Stops with PCI_STOP#
assertion
0
Byte 7 Vendor ID/ Revision ID Register
Bit Name Description Type 0 1 Default
7 Rev Code Bit 3 R0
6 Rev Code Bit 2 R0
5 Rev Code Bit 1 R0
4 Rev Code Bit 0 R1
3 Vendor ID bit 3 R0
2 Vendor ID bit 2 R0
1 Vendor ID bit 1 R0
0 Vendor ID bit 0 R1
Byte 8 Device ID & Output Enable Register
Bit Name Description Type 0 1 Default (TSSOP) Default (MLF)
7
Device_ID3 R00
6
Device_ID2 R00
5
Device_ID1 R00
4
Device_ID0 R10
3 Reserved Reserved RW
--
00
2 Reserved
Reserved
RW
--
00
1
27MHz_nonSS/SE1_OE
Output enable for SE1
RW Disabled Enabled
11
0
27MHz_SS/SE2_OE
Output enable for SE2
RW Disabled Enabled
11
Byte 9 Test and Output Control Register
Bit Name Description Type 0 1 Default
7 PCIF5 STOP EN Allows control of PCIF5 with assertion of PCI_STOP# RW Free running
Stops with PCI_STOP#
assertion
0
6 TME_Readback
Truested Mode Enable
(
TME
)
stra
p
status
R
normal o
p
eration no overclockin
g
TME latch
5
Reserved Reserved
RW
--
1
4 Test Mode Select
Allows test select, i
g
nores REF/FSC/TestSel
RW
Out
p
uts HI-Z Out
p
uts = REF/N
0
3 Test Mode Entr
y
Allows entr
y
into test mode, i
g
nores FSB/TestMode
RW
Normal o
p
eration Test mode
0
2 CPU IO_VOUT2
CPU IO Out
p
ut Volta
g
e Select
(
Most Si
g
nificant Bit
)
RW 1
1 CPU IO_VOUT1
CPU IO Out
p
ut Volta
g
e Select
RW 0
0 CPU IO_VOUT0 CPU IO Output Voltage Select (Least Significant Bit) RW 1
Byte 10 Output Control Register
Bit Name Description Type 0 1 Default
7
27_SEL Latch Readback Readback of 27_Select latch
R
Dot96/ LCD_SS /SE SRC0/ 27MHz 27_SEL latch
6 PCI4 STOP EN Allows control of PCI4 with assertion of PCI_STOP# RW Free running
Stops with PCI_STOP#
assertion
1
5 PCI3 STOP EN Allows control of PCI3 with assertion of PCI_STOP# RW Free running
Stops with PCI_STOP#
assertion
1
4 PCI2 STOP EN Allows control of PCI2 with assertion of PCI_STOP# RW Free running
Stops with PCI_STOP#
assertion
1
3 PCI1 STOP EN Allows control of PCI1 with assertion of PCI_STOP# RW Free running
Stops with PCI_STOP#
assertion
1
2 PCI0 STOP EN Allows control of PCI0 with assertion of PCI_STOP# RW Free running
Stops with PCI_STOP#
assertion
1
1 CPU1 Sto
p
Enable
Enables control of CPU1 with CPU_STOP#
RW
Free Runnin
g
Sto
pp
able
1
0 CPU0 Stop Enable Enables control of CPU0 with CPU_STOP# RW Free Running Stoppable 1
See Table 3: V_IO Selection
(Default is 0.8V)
Revision ID
Vendor specific
Vendor ID
ICS is 0001, binary
Table of Device identifier codes, used for differentiating between
CK505 package options, etc.
See Device ID Table 4
IDT
®
64-pin CK505 Compatible Clock w/Fully Integrated Voltage Regulator + Integrated Series Resistor 1533B—01/06/15
9LRS3165B
64-pin CK505 Compatible Clock w/Fully Integrated Voltage Regulator + Integrated Series Resistor
21
Byte 11 iAMT/CPU2 Control Register
Bit Name Description Type 0 1 Default
7 Reserved
Reserved
RW
--
0
6 Reserved
Reserved
RW
--
0
5 Reserved
Reserved
RW
--
0
4 Reserved
Reserved
RW
--
0
3 CPU2_AMT_EN M1 mode clk enable, onl
y
if ITP_EN=1 RW
Disable Enable
0
2 CPU1_AMT_EN M1 mode clk enable RW
Disable Enable
1
1 Reserved Reserved RW
--
0
0
CPU2 Stop Enable Enables control of CPU2 with CPU_STOP# RW Free Running Stoppable 1
Byte 12 Byte Count Register
Bit Name Description Type 0 1 Default
7
Reserved Reserved RW - - 0
6
Reserved Reserved RW - - 0
5
BC5 RW - - 0
4
BC4 RW - - 0
3
BC3 RW - - 1
2
BC2 RW - - 1
1
BC1 RW - - 0
0
BC0 RW - - 1
Byte 13 Single Ended Output Slew Rate Control Register
Bit Name Description RW 0 1 Default
7
REF RW 00 = Hi-Z 01 = 1.4 V/ns 0
6
REF RW 10 = 2.0 V/ns 11 = 2.4 V/ns 1
5
27M_FIX RW 00 = Hi-Z 01 = 1.4 V/ns 0
4
27M_FIX RW 10 = 2.0 V/ns 11 = 2.4 V/ns 1
3
27M_SS RW 00 = Hi-Z 01 = 1.4 V/ns 0
2
27M_SS RW 10 = 2.0 V/ns 11 = 2.4 V/ns 1
1
Reserved Reserved RW - - 0
0
Reserved Reserved RW - - 0
Byte 14 Reserved
Bit Name Description Type 0 1 Default
7
Reserved Reserved RW - -
X
6
Reserved Reserved RW - -
X
5
Reserved Reserved RW - -
X
4
Reserved Reserved RW - -
X
3
Reserved Reserved RW - -
X
2
Reserved Reserved RW - -
X
1
Reserved Reserved RW - -
X
0 Reserved Reserved RW - -
X
Byte 15 Reserved
Bit Name Description Type 0 1
Default
7
Reserved Reserved RW - -
X
6
Reserved Reserved RW - -
X
5
Reserved Reserved RW - -
X
4
Reserved Reserved RW - -
X
3
Reserved Reserved RW - -
X
2
Reserved Reserved RW - -
X
1
Reserved Reserved RW - -
X
0 Reserved Reserved RW - -
X
Byte 16 Reserved
Bit Name Description Type 0 1
Default
7
Reserved Reserved RW - -
X
6
Reserved Reserved RW - -
X
5
Reserved Reserved RW - -
X
4
Reserved Reserved RW - -
X
3
Reserved Reserved RW - - X
2
Reserved Reserved RW - - X
1
Reserved Reserved RW - - X
0 Reserved Reserved RW - - X
Read Back byte count register,
max bytes = 32
Slew Rate Control
Slew Rate Control
Slew Rate Control
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28

9LRS3165BKLF

Mfr. #:
Buy 9LRS3165BKLF
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner PC MAIN CLOCK
Lifecycle:
New from this manufacturer.
Delivery:
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