IDT
®
64-pin CK505 Compatible Clock w/Fully Integrated Voltage Regulator + Integrated Series Resistor 1533B—01/06/15
9LRS3165B
64-pin CK505 Compatible Clock w/Fully Integrated Voltage Regulator + Integrated Series Resistor
7
MLF Pin Description (Continued)
PIN # PIN NAME TYPE DESCRIPTION
24 27FIX/LCDT/SRCT_LR1/SE1 OUT
Single-ended 3.3V 27MHz fix clock output / True clock of differential SRC1 or LCD
clock pair / Single ended 3.3V peripheral clock output. The default output selection
is determined by the SEL_27 default latch value. See below:
27_SEL=0
: LCD100 with -0.5% down spread is selected as default. LCD100 spread
percentage can be adjusted OR output can be changed to SRC or 3.3V single-ended
peripheral clock output via SMBUs B1b[4:1].
27_SEL=1
: Single-ended 27FIX output is selected.
25 27SS/LCDC/SRCC_LR1/SE2 OUT
Single-ended 3.3V 27MHz fix clock output / Complementary clock of differential
SRC1 or LCD clock pair / Single ended 3.3V peripheral clock output. The default
output selection is determined by the SEL_27 default latch value. See below:
27_SEL=0
: LCD100 with -0.5% down spread is selected as default. LCD100 spread
percentage can be adjusted OR output can be changed to SRC or 3.3V single-ended
peripheral clock output via SMBUs B1b[4:1].
27_SEL=1: Single-ended 27SS output is selected with -0.5% down spread as
default. Spread percentage can be adjusted via SMBus B1b[4:1].
26
GND
PWR Ground
in for SRC / SE1 and SE2 clocks, PLL3.
27
VDDPLL3I/O
PWR 1.05V to 3.3V from external
ower su
l
28
SRCT_LR2/SATACLKT
OUT True clock of differential SRC/SATA clock pair.
29
SRCC_LR2/SATACLKC
OUT Com
lement clock of differential SRC/SATA clock
air.
30
GNDSRC
PWR Ground
in for SRC clocks.
31
SRCT_LR3/CR#_C
I/O
True clock of differential SRC clock pair/ Clock Request control C for either SRC0 or
SRC2 pair
The power-up default is SRCCLK3 output, but this pin may also be used as a Clock
Request control of SRC pair 0 or SRC pair 2 via SMBus. Before configuring this pin
as a Clock Request Pin, the SRC3 output must first be disabled in byte 4, bit 7 of
SMBus address space . After the SRC3 output is disabled, the pin can then be set to
serve as a Clock Request pin for either SRC pair 2 or pair 0 using the CR#_C_EN bit
located in byte 5 of SMBUs address space.
Byte 5, bit 3
0 = SRC3 enabled (default)
1= CR#_C enabled.
Byte 5, bit 2 controls whether CR#_C controls SRC0 or SRC2 pair
Byte 5, bit 2
0 = CR#_C controls SRC0 pair (default),
1= CR#_C controls SRC2 pair
32
SRCC_LR3/CR#_D
I/O
Complementary clock of differential SRC clock pair/ Clock Request control D for
either SRC1 or SRC4 pair
The power-up default is SRCCLK3 output, but this pin may also be used as a Clock
Request control of SRC pair 1 or SRC pair 4 via SMBus. Before configuring this pin
as a Clock Request Pin, the SRC3 output must first be disabled in byte 4, bit 7 of
SMBus address space . After the SRC3 output is disabled, the pin can then be set to
serve as a Clock Request pin for either SRC pair 1 or pair 4 using the CR#_D_EN bit
located in byte 5 of SMBUs address space.
Byte 5, bit 1
0 = SRC3 enabled (default)
1= CR#_D enabled.
Byte 5, bit 0 controls whether CR#_D controls SRC1 or SRC4 pair
Byte 5, bit 0
0 = CR#_D controls SRC1 pair (default),
1= CR#_D controls SRC4 pair
33
VDDSRCI/O
PWR 1.05V to 3.3V from external
ower su
l
34
SRCT_LR4
I/O True clock of differential SRC clock
air 4
35
SRCC_LR4
I/O Com
lement clock of differential SRC clock
air 4
36
GNDSRC
PWR Ground
in for SRC clocks.
37
SRCT_LR9
OUT True clock of differential SRC clock pair.
38
SRCC_LR9
OUT Com
lement clock of differential SRC clock
air.
39
SRCC_LR11/CR#_G
I/O
SRC11 complement /Clock Request control for SRC9 pair
The power-up default is SRC11#, but this pin may also be used as a Clock Request
control of SRC9 via SMBus. Before configuring this pin as a Clock Request Pin, the
SRC11 output pair must first be disabled in byte 3, bit 7 of SMBus configuration
space After the SRC11 output is disabled (high-Z), the pin can then be set to serve
as a Clock Request for SRC9 pair using byte 6, bit 5 of SMBus configuration space
Byte 6, bit 5
0 = SRC11# enabled (default)
1= CR#_G controls SRC9
