AFBR-5103TZ Datasheet AFBR-5103PZ, AFBR-5103Z, AFBR-5103ATZ | P7-P9

TRANSCEIVER RELATIVE OPTICAL POWER BUDGET

AT CONSTANT BER (dB)

0 200

3.0

SIGNAL RATE (MBd)

25 75 100 125

2.5

2.0

1.5

1.0

175

0.5

50 150

CONDITIONS:

1. PRBS 2

-1

2. DATA SAMPLED AT CENTER OF DATA SYMBOL.

3. BER = 10

-6

4. T

= 25˚ C

5. V

= 5 V

6. INPUT OPTICAL RISE/FALL TIMES = 1.0/2.1 ns.

Figure 5. Transceiver Relative Optical Power Budget at Constant BER

vs. Signaling Rate.

Figure 6. Bit Error Rate vs. Relative Receiver Input Optical Power.

BIT ERROR RATE

-6 4

1 x 10

-2

RELATIVE INPUT OPTICAL POWER - dB

-4 2-2

1 x 10

-4

1 x 10

-6

1 x 10

-8

2.5 x 10

-10

1 x 10

-11

AFBR-5103Z/5103TZ SERIES

CONDITIONS:

1. 125 MBd

2. PRBS 2

-1

3. CENTER OF SYMBOL SAMPLING.

4. T

= 25˚ C

5. V

= 5 V

6. INPUT OPTICAL RISE/FALL TIMES = 1.0/2.1 ns.

CENTER OF SYMBOL

1 x 10

-12

1 x 10

-7

1 x 10

-5

1 x 10

-3

Transceiver Jitter Performance

The Avago Technologies 1300 nm transceivers are de-

signed to operate per the system jitter allocations stated

in Tables E1 of Annexes E of the FDDI PMD and LCF-PMD

standards.

The Avago Technologies 1300 nm transmitters will toler-

ate the worst case input electrical jitter allowed in these

tables without violating the worst case output jitter re-

quirements of Sections 8.1 Active Output Interface of the

FDDI PMD and LCF-PMD standards.

The Avago Technologies 1300 nm receivers will tolerate

the worst case input optical jitter allowed in Sections 8.2

Active Input Interface of the FDDI PMD and LCF-PMD

standards without violating the worst case output elec-

trical jitter allowed in the Tables E1 of the Annexes E.

The jitter speci cations stated in the following 1300 nm

transceiver speci cation tables are derived from the

values in Tables E1 of Annexes E. They represent the worst

case jitter contribution that the trans ceivers are allowed

to make to the overall system jitter without violating the

Annex E allocation example. In practice the typical con-

tribution of the Avago Technologies trans ceivers is well

below these maximum allowed amounts.

Recommended Handling Precautions

Avago Technologies recommends that normal static pre-

cautions be taken in the handling and assembly of these

transceivers to prevent damage which may be induced

by electrostatic discharge (ESD). The AFBR-5100Z series

of transceivers meet MIL-STD-883C Method 3015.4 Class

2 products.

Care should be used to avoid shorting the receiver data

or signal detect outputs directly to ground without

proper current limiting impedance.

Figure 7. Recommended Decoupling and Termination Circuits

NO INTERNAL CONNECTION NO INTERNAL CONNECTION

AFBR-510XZ

TOP VIEW

RD RD SD V

TD TD V

123456789

C1 C2

L1 L2

R2 R3

R1 R4

C3 C4

R10

FILTER

AT V

PINS

TRANSCEIVER

R5 R7

R6 R8

RD RD SD V

TD TD

TERMINATION

AT PHY

DEVICE

INPUTS

NOTES:

THE SPLIT-LOAD TERMINATIONS FOR ECL SIGNALS NEED TO BE LOCATED AT THE INPUT

OF DEVICES RECEIVING THOSE ECL SIGNALS. RECOMMEND 4-LAYER PRINTED CIRCUIT

BOARD WITH 50 OHM MICROSTRIP SIGNAL PATHS BE USED.

TERMINATION

AT TRANSCEIVER

INPUTS

R1 = R4 = R6 = R8 = R10 = 130 OHMS.

R2 = R3 = R5 = R7 = R9 = 82 OHMS.

C1 = C2 = C3 = C5 = C6 = 0.1 µF.

C4 = 10 µF.

Rx Rx Tx Tx

Rx Tx

Solder and Wash Process Compatibility

The transceivers are delivered with protective process

plugs inserted into the duplex SC or duplex ST connector

receptacle.

This process plug protects the optical subassemblies

during wave solder and aqueous wash processing and

acts as a dust cover during shipping.

These transceivers are compat ible with either industry

standard wave or hand solder processes.

Shipping Container

The transceiver is packaged in a shipping container de-

signed to protect it from mechanical and ESD damage

during shipment or storage.

Board Layout - Decoupling Circuit and Ground Planes

It is important to take care in the layout of your circuit

board to achieve optimum perform ance from these

transceivers. Figure 7 provides a good example of a

schematic for a power supply decoupling circuit that

works well with these parts. It is further recommend-

ed that a contiguous ground plane be provided in the

circuit board directly under the transceiver to provide

a low inductance ground for signal return current. This

recommen da tion is in keeping with good high frequen-

cy board layout practices.

Board Layout - Hole Pattern

The Avago Technologies trans ceiver complies with the

circuit board “Common Transceiver Footprint” hole

pattern de ned in the original multisource announce-

ment which de ned the 1x9 package style. This drawing

is repro duced in Figure 8 with the addition of ANSI

Y14.5M compliant dimensioning to be used as a guide in

the mechani cal layout of your circuit board.

Board Layout - Mechanical

For applications providing a choice of either a duplex SC

or a duplex ST connector interface, while utilizing the

same pinout on the printed circuit board, the ST port

needs to protrude from the chassis panel a minimum of

9.53 mm for su cient clearance to install the ST connec-

tor.

Please refer to Figure 8A for a mechanical layout detailing

the recommended location of the duplex SC and duplex

ST trans ceiver packages in relation to the chassis panel.

For both shielded design options, Figure 8b identi es

front panel aperture dimensions.

Figure 8. Recommended Board Layout Hole Pattern

Regulatory Compliance

These transceiver products are intended to enable com-

mercial system designers to develop equipment that

complies with the various international regulations gov-

erning certi ca tion of Information Technology Equip-

ment. See the Regulatory Compliance Table for details.

Additional information is available from your Avago

Technologies sales representative.

Electrostatic Discharge (ESD)

There are two design cases in which immunity to ESD

damage is important.

The  rst case is during handling of the transceiver prior

to mount ing it on the circuit board. It is important to

use normal ESD handling precautions for ESD sensitive

devices. These precautions include using grounded wrist

straps, work benches, and  oor mats in ESD controlled

areas.

The second case to consider is static discharges to the

exterior of the equipment chassis con taining the trans-

ceiver parts. To the extent that the duplex SC connector

is exposed to the outside of the equipment chassis it may

be subject to whatever ESD system level test criteria that

the equipment is intended to meet.

(8X)

2.54

.100

20.32

.800

20.32

.800

1.9 ± 0.1

.075 ± .004

(2X)

∅

¯0.000

0.8 ± 0.1

.032 ± .004

(9X)

∅

¯0.000

-A-

TOP VIEW

Electromagnetic Interference (EMI)

Most equipment designs utilizing these high speed

trans ceivers from Avago Technologies will be required

to meet the require ments of FCC in the United States,

CENELEC EN55022 (CISPR 22) in Europe and VCCI in

Japan.

These products are suitable for use in designs ranging

from a desktop computer with a single transceiver to a

concentrator or switch product with a large number of

transceivers.

In all well-designed chassis, two 0.5” holes for ST connec-

tors to pro trude through will provide 4.6 dB more shield-

ing than one 1.2” duplex SC rectangular cutout. Thus, in

a well-designed chassis, the duplex ST 1x9 transceiver

emissions will be identical to the duplex SC 1x9 trans-

ceiver emissions.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P20

AFBR-5103TZ

Mfr. #:

Buy AFBR-5103TZ

Manufacturer:

Broadcom / Avago

Description:

TXRX OPT 1X9 100MBPS DUPL ST SIP

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

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AFBR-5103TZ

AFBR-5103TZ

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