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7007L35J

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22
13
IDT7007S/L
High-Speed 32K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
(6)
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = V
IH)".
2. To ensure that the earlier of the two ports wins.
3. t
BDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6. 'X' in part numbers indicates power rating (S or L).
Symbol Parameter
7007X15
Com'l Only
7007X20
Com'l & Ind
7007X25
Com'l, Ind
& Military
UnitMin. Max. Min. Max. Min. Max.
BUSY TIMING (M/S=V
IH
)
t
BAA
BUSY Access Time from Address Match
____
15
____
20
____
20 ns
t
BDA
BUSY Disable Time from Address Not Matched
____
15
____
20
____
20 ns
t
BAC
BUSY Access Time from Chip Enable Low
____
15
____
20
____
20 ns
t
BDC
BUSY Access Time from Chip Enable High
____
15
____
17
____
17 ns
t
APS
Arbitration Priority Set-up Time
(2 )
5
____
5
____
5
____
ns
t
BDD
BUSY Disable to Valid Data
(3 )
____
18
____
30
____
30 ns
t
WH
Write Hold After BUSY
(5 )
12
____
15
____
17
____
ns
BUSY TIMING (M/S=V
IL
)
t
WB
BUSY Input to Write
(4 )
0
____
0
____
0
____
ns
t
WH
Write Hold After BUSY
(5 )
12
____
15
____
17
____
ns
PORT-TO-PORT DELAY TIMING
t
WDD
Write Pulse to Data Delay
(1 )
____
30
____
45
____
50 ns
t
DD D
Write Data Valid to Read Data Delay
(1)
____
25
____
30
____
35 ns
2940 tbl 14a
Symbol Parameter
7007X35
Com'l, Ind
& Military
7007X55
Com'l, Ind
& Military
UnitMin. Max. Min. Max.
BUSY TIMING (M/S=V
IH
)
t
BAA
BUSY Access Time from Address Match
____
20
____
45 ns
t
BDA
BUSY Disable Time from Address Not Matched
____
20
____
40 ns
t
BAC
BUSY Access Time from Chip Enable Low
____
20
____
40 ns
t
BDC
BUSY Access Time from Chip Enable High
____
20
____
35 ns
t
APS
Arbitration Priority Set-up Time
(2 )
5
____
5
____
ns
t
BDD
BUSY Disable to Valid Data
(3 )
____
35
____
40 ns
t
WH
Write Hold After BUSY
(5 )
25
____
25
____
ns
BUSY TIMING (M/S=V
IL
)
t
WB
BUSY Input to Write
(4 )
0
____
0
____
ns
t
WH
Write Hold After BUSY
(5 )
25
____
25
____
ns
PORT-TO-PORT DELAY TIMING
t
WDD
Write Pulse to Data Delay
(1 )
____
60
____
80 ns
t
DD D
Write Data Valid to Read Data Delay
(1)
____
45
____
65 ns
2940 tbl 14b
IDT7007S/L
High-Speed 32K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
14
Timing Waveform of Write with Port-to-Port Read and BUSY
(2,5)
(M/S = VIH)
(4)
Timing Waveform of Write with BUSY (M/S = VIL)
NOTES:
1. t
WH must be met for both BUSY input (SLAVE) and output (MASTER).
2. BUSY is asserted on port "B" blocking R/W
"B", until BUSY"B" goes HIGH.
2940 drw 13
t
DW
t
APS
ADDR
"A"
t
WC
DATA
OUT "B"
MATCH
t
WP
R/W
"A"
DATA
IN "A"
ADDR
"B"
t
DH
VALID
(1)
MATCH
BUSY
"B"
t
BDA
VALID
t
BDD
t
DDD
(3)
t
WDD
NOTES:
1. To ensure that the earlier of the two ports wins. t
APS is ignored for M/S = VIL (SLAVE).
2. CE
L = CER = VIL
3. OE = VIL for the reading port.
4. If M/S = V
IL (SLAVE), then BUSY is an input (BUSY"A" = VIH and BUSY"B" = "don't care", for this example).
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
2940 drw 14
R/W
"A"
BUSY
"B"
t
WP
t
WB
R/W
"B"
t
WH
(1)
(2)
,
15
IDT7007S/L
High-Speed 32K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
Waveform of BUSY Arbitration Controlled by CE Timing
(1)
(M/S = VIH)
Waveform of BUSY Arbitration Cycle Controlled by Address Match
Timing
(1)
(M/S = VIH)
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. If t
APS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.
NOTES:
1. 'X' in part numbers indicates power rating (S or L).
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
(1,2)
2940 drw 15
ADDR
"A"
and
"B"
ADDRESSES MATCH
CE
"A"
CE
"B"
BUSY
"B"
t
APS
t
BAC
t
BDC
(2)
2940 drw 16
ADDR
"A"
ADDRESS "N"
ADDR
"B"
BUSY
"B"
t
APS
t
BAA
t
BDA
(2)
MATCHING ADDRESS "N"
7007X15
Com'l Only
7007X20
Com'l & Ind
7007X25
Com'l, Ind
& Military
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
INTERRUPT TIMING
t
AS
Address Set-up Time 0
____
0
____
0
____
ns
t
WR
Write Recovery Time 0
____
0
____
0
____
ns
t
INS
Interrupt Set Time
____
15
____
20
____
20 ns
t
INR
Interrupt Reset Time
____
15
____
20
____
20 ns
2940 tbl 15a
7007X35
Com'l, Ind
& Military
7007X55
Com'l, Ind
& Military
UnitSymbol Parameter Min. Max. Min. Max.
INTERRUPT TIMING
t
AS
Address Set-up Time 0
____
0
____
ns
t
WR
Write Recovery Time 0
____
0
____
ns
t
INS
Interrupt Set Time
____
25
____
40 ns
t
INR
Interrupt Reset Time
____
25
____
40 ns
2940 tbl 15b
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22

7007L35J

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Description:
SRAM 256K(32K X 8) DUAL PORT
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