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7007L35J

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22
7
IDT7007S/L
High-Speed 32K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(1)
(con't.) (VCC = 5.0V ± 10%)
NOTES:
1. 'X' in part numbers indicates power rating (S or L)
2. V
CC = 5V, TA = +25°C, and are not production tested. ICCDC = 120mA (Typ.)
3. At f = f
MAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using
“AC Test Conditions” of input levels of GND to 3V.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
Symbol Parameter Test Condition Version
7007X35
Com'l, Ind
& Military
7007X55
Com'l, Ind
& Military
UnitTyp.
(2)
Max. Typ.
(2 )
Max.
I
CC
Dynamic Operating Current
(Both Ports Active)
CE = V
IL
, Outputs Disabled
SEM = V
IH
f = f
MAX
(3 )
COM'L S
L
160
160
295
255
150
150
270
230
mA
MIL &
IND
S
L
160
160
335
295
150
150
310
270
I
SB1
Standby Current
(Both Ports - TTL Level
Inputs)
CE
L
= CE
R
= V
IH
SEM
R
= SEM
L
= V
IH
f = f
MAX
(3 )
COM'L S
L
20
20
85
60
20
20
85
60
mA
MIL &
IND
S
L
20
20
100
80
13
13
100
80
I
SB2
Standby Current
(One Port - TTL Level Inputs)
CE
"A"
= V
IL
and CE
"B"
= V
IH
(5 )
Active Port Outputs Disabled,
f=f
MAX
(3 )
SEM
R
= SE M
L
= V
IH
COM'L
S
L
95
95
185
155
85
85
165
135
mA
MIL &
IND
S
L
95
95
215
185
85
85
195
165
I
SB3
Full Standby Current (Both
Ports - All CMOS Level
Inputs)
Both Ports CE
L
and
CE
R
> V
CC
- 0.2V
V
IN
> V
CC
- 0.2V or
VIN <
0.2V, f = 0
(4 )
SEM
R
= SEM
L
> V
CC
- 0.2V
COM'L S
L
1.0
0.2
15
5
1.0
0.2
15
5
mA
MIL &
IND
S
L
1.0
0.2
30
10
1.0
0.2
30
10
I
SB4
Full Standby Current
(One Port - All CMOS Level
Inputs)
CE
"A"
< 0.2V and
CE
"B"
> V
CC
- 0.2V
(5 )
SEM
R
= SEM
L
> V
CC
- 0.2V
V
IN
> V
CC
- 0.2V or V
IN
< 0.2V
Active Port Outputs Disabled
f = f
MAX
(3 )
COM'L
S
L
90
90
160
135
80
80
135
110
mA
MIL &
IND
S
L
90
90
190
165
80
80
165
140
2940 tbl 10
IDT7007S/L
High-Speed 32K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
8
NOTES:
1. Transition is measured 0mV from Low- or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = V
IL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL.
4. 'X' in part numbers indicates power rating (S or L).
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
(4)
AC Test Conditions
Figure 2. Output Test Load
(for tLZ, tHZ, tWZ, tOW)
* Including scope and jig.
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
5ns Max.
1.5V
1.5V
Figures 1 and 2
2940 tbl 11
Figure 1. AC Output Test Load
2940 drw 06
893Ω
30pF
347Ω
5V
DATA
OUT
BUSY
INT
893Ω
5pF*
347Ω
5V
DATA
OUT
2940 drw 05
7007X15
Com'l Only
7007X20
Com'l & Ind
7007X25
Com'l, Ind
& Military
UnitSymbol Parameter Min.Max.Min.Max.Min.Max.
READ CYCLE
t
RC
Read Cycle Time 15
____
20
____
25
____
ns
t
AA
Address Access Time
____
15
____
20
____
25 ns
t
ACE
Chip Enable Access Time
(3)
____
15
____
20
____
25 ns
t
AOE
Output Enable Access Time
____
10
____
12
____
13 ns
t
OH
Output Hold from Address Change 3
____
3
____
3
____
ns
t
LZ
Output Low-Z Time
(1,2)
3
____
3
____
3
____
ns
t
HZ
Output High-Z Time
(1,2)
____
10
____
12
____
15 ns
t
PU
Chip Enable to Power Up Time
(2 )
0
____
0
____
0
____
ns
t
PD
Chip Disable to Power Down Time
(2 )
____
15
____
20
____
25 ns
t
SOP
Semaphore Flag Update Pulse (OE or SEM)10
____
10
____
12
____
ns
t
SAA
Semaphore Address Access Time
____
15
____
20
____
25 ns
2940 tbl 12a
7007X35
Com'l, Ind
& Military
7007X55
Com'l, Ind
& Military
UnitSymbol Parameter Min.Max.Min.Max.
READ CYCLE
t
RC
Read Cycle Time 35
____
55
____
ns
t
AA
Address Access Time
____
35
____
55 ns
t
ACE
Chip Enable Access Time
(3 )
____
35
____
55 ns
t
AOE
Output Enable Access Time
____
20
____
30 ns
t
OH
Output Hold from Address Change 3
____
3
____
ns
t
LZ
Output Low-Z Time
(1,2)
3
____
3
____
ns
t
HZ
Output High-Z Time
(1,2)
____
15
____
25 ns
t
PU
Chip Enable to Power Up Time
(2 )
0
____
0
____
ns
t
PD
Chip Disable to Power Down Time
(2 )
____
35
____
50 ns
t
SOP
Semaphore Flag Update Pulse (OE or SEM)15
____
15
____
ns
t
SAA
Semaphore Address Access Time
____
35
____
55 ns
2940 tbl 12b
9
IDT7007S/L
High-Speed 32K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
Timing of Power-Up Power-Down
Waveform of Read Cycles
(5)
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is de-asserted first CE or OE.
3. t
BDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY
has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last t
AOE, tACE, tAA or tBDD.
5. SEM = V
IH.
t
RC
R/W
CE
ADDR
t
AA
OE
2940 drw 07
(4)
t
ACE
(4)
t
AOE
(4)
(1)
t
LZ
t
OH
(2)
t
HZ
(3,4)
t
BDD
DATA
OUT
BUSY
OUT
VALID DATA
(4)
CE
2940 drw 08
t
PU
I
CC
I
SB
t
PD
,
50%
50%
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7007L35J

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Description:
SRAM 256K(32K X 8) DUAL PORT
Lifecycle:
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