IDT7007S/L
High-Speed 32K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
16
Truth Table III — Interrupt Flag
(1)
Waveform of Interrupt Timing
(1)
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. See Interrupt Truth Table III.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
NOTES:
1. Assumes BUSY
L = BUSYR =VIH.
2. If BUSY
L = VIL, then no change.
3. If BUSY
R = VIL, then no change.
2940 drw 17
ADDR
"A"
INTERRUPT SET ADDRESS
CE
"A"
R/W
"A"
t
AS
t
WC
t
WR
(3)
(4)
t
INS
(3)
INT
"B"
(2)
2940 drw 18
ADDR
"B"
INTERRUPT CLEAR ADDRESS
CE
"B"
OE
"B"
t
AS
t
RC
(3)
t
INR
(3)
INT
"B"
(2)
Left Port Right Port
FunctionR/W
L
CE
L
OE
L
A
14L
-A
0L
INT
L
R/W
R
CE
R
OE
R
A
14R
-A
0R
INT
R
LLX7FFFXXXX X L
(2)
Set Right INT
R
Flag
XXX X XXLL7FFFH
(3 )
Reset Right INT
R
Flag
XXX X L
(3)
L L X 7FFE X Set Left INT
L
Flag
XLL7FFEH
(2 )
XXX X XReset Left INT
L
Flag
2940 tbl 16
17
IDT7007S/L
High-Speed 32K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
Truth Table IV — Address BUSY
Arbitration
NOTES:
1. Pins BUSY
L and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the IDT7007 are
push-pull, not open drain outputs. On slaves the BUSY input internally inhibits writes.
2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address
and enable inputs of this port. If t
APS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSY
L outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored
when BUSY
R outputs are driving LOW regardless of actual logic level on the pin.
Truth Table V — Example of Semaphore Procurement Sequence
(1,2,3)
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7007.
2. There are eight semaphore flags written to via I/O
5(I/O0 - I/O7) and read from all I/O0. These eight semaphores are addressed by A0 - A2.
3. CE = V
IH, SEM = VIL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.
Functional Description
The IDT7007 provides two ports with separate control, address and
I/O pins that permit independent access for reads or writes to any location
in memory. The IDT7007 has an automatic power down feature controlled
by CE. The CE controls on-chip power down circuitry that permits the
respective port to go into a standby mode when not selected (CE HIGH).
When a port is enabled, access to the entire memory array is permitted.
INTERRUPTS
If the user chooses the interrupt function, a memory location (mail box
or message center) is assigned to each port. The left port interrupt flag
(INTL) is asserted when the right port writes to memory location 7FFE
(HEX), where a write is defined as CE = R/W = VIL per the Truth Table.
The left port clears the interrupt through access of address location 7FFE
when CE
R = OER = VIL, R/W is a "don't care". Likewise, the right port
interrupt flag (INTR) is asserted when the left port writes to memory location
7FFF (HEX) and to clear the interrupt flag (INTR), the right port must read
the memory location 7FFF. The message (8 bits) at 7FFE or 7FFF is user-
defined since it is an addressable SRAM location. If the interrupt function
is not used, address locations 7FFE and 7FFF are not used as mail boxes,
but as part of the random access memory. Refer to Table III for the interrupt
operation.
Busy Logic
Busy Logic provides a hardware indication that both ports of the RAM
have accessed the same location at the same time. It also allows one of
the two accesses to proceed and signals the other side that the RAM is
Inputs Outputs
Function
CE
L
CE
R
A
OL
-A
14L
A
OR
-A
14R
BUSY
L
(1)
BUSY
R
(1)
XXNO MATCH H H Normal
H X MATCH H H Normal
X H MATCH H H Normal
L L MATCH (2) (2) Write Inhibit
(3)
2940 tbl 17
Functions D
0
- D
7
Left D
0
- D
7
Right Status
No Action 1 1 Semaphore free
Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token
Right Port Writes "0" to Semaphore 0 1 No change. Right side has no write access to semaphore
Left Port Writes "1" to Semaphore 1 0 Right port obtains semaphore token
Left Port Writes "0" to Semaphore 1 0 No change. Left port has no write access to semaphore
Right Port Writes "1" to Semaphore 0 1 Left port obtains semaphore token
Left Port Writes "1" to Semaphore 1 1 Semaphore free
Right Port Writes "0" to Semaphore 1 0 Right port has semaphore token
Right Port Writes "1" to Semaphore 1 1 Semaphore free
Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token
Left Port Writes "1" to Semaphore 1 1 Semaphore free
2940 tbl 18
IDT7007S/L
High-Speed 32K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges
18
“busy”. The BUSY pin can then be used to stall the access until the
operation on the other side is completed. If a write operation has been
attempted from the side that receives a BUSY indication, the write signal
is gated internally to prevent the write from proceeding.
The use of BUSY logic is not required or desirable for all applications.
In some cases it may be useful to logically OR the BUSY outputs together
and use any BUSY indication as an interrupt source to flag the event of
an illegal or illogical operation. If the write inhibit function of BUSY logic is
not desirable, the BUSY logic can be disabled by placing the part in slave
mode with the M/S pin. Once in slave mode the BUSY pin operates solely
as a write inhibit input pin. Normal operation can be programmed by tying
the BUSY pins HIGH. If desired, unintended write operations
can be prevented to a port by tying the BUSY pin for that port LOW.
The BUSY outputs on the IDT 7007 RAM in master mode, are push-
pull type outputs and do not require pull up resistors to operate. If these
RAMs are being expanded in depth, then the BUSY indication for the
resulting array requires the use of an external AND gate.
Width Expansion with Busy Logic
Master/Slave Arrays
Semaphores
The IDT7007 is an extremely fast Dual-Port 16K x 8 CMOS Static RAM
with an additional 8 address locations dedicated to binary semaphore flags.
These flags allow either processor on the left or right side of the Dual-Port
RAM to claim a privilege over the other processor for functions defined by
the system designer’s software. As an example, the semaphore can be
used by one processor to inhibit the other from accessing a portion of the
Dual-Port RAM or any other shared resource.
The Dual-Port RAM features a fast access time, and both ports are
completely independent of each other. This means that the activity on the
left port in no way slows the access time of the right port. Both ports are
identical in function to standard CMOS Static RAM and can be read from,
or written to, at the same time with the only possible conflict arising from the
simultaneous writing of, or a simultaneous READ/WRITE of, a non-
semaphore location. Semaphores are protected against such ambiguous
situations and may be used by the system program to avoid any conflicts
in the non-semaphore portion of the Dual-Port RAM. These devices have
an automatic power-down feature controlled by CE, the Dual-Port RAM
enable, and SEM, the semaphore enable. The CE and SEM pins control
on-chip power down circuitry that permits the respective port to go into
standby mode when not selected. This is the condition which is shown in
Truth Table I where CE and SEM are both HIGH.
Systems which can best use the IDT7007 contain multiple proces-
sors or controllers and are typically very high-speed systems which
are software controlled or software intensive. These systems can
benefit from a performance increase offered by the IDT7007 hardware
semaphores, which provide a lockout mechanism without requiring
complex programming.
Software handshaking between processors offers the maximum in
system flexibility by permitting shared resources to be allocated in varying
configurations. The IDT7007 does not use its semaphore flags to control
any resources through hardware, thus allowing the system designer total
flexibility in system architecture.
An advantage of using semaphores rather than the more common
methods of hardware arbitration is that wait states are never incurred in
either processor. This can prove to be a major advantage in very high-
speed systems.
How the Semaphore Flags Work
The semaphore logic is a set of eight latches which are independent
of the Dual-Port RAM. These latches can be used to pass a flag, or token,
from one port to the other to indicate that a shared resource is in use. The
semaphores provide a hardware assist for a use assignment method
called “Token Passing Allocation.” In this method, the state of a semaphore
latch is used as a token indicating that shared resource is in use. If the left
processor wants to use this resource, it requests the token by setting the
latch. This processor then verifies its success in setting the latch by reading
it. If it was successful, it proceeds to assume control over the shared
resource. If it was not successful in setting the latch, it determines that the
right side processor has set the latch first, has the token and is using the
shared resource. The left processor can then either repeatedly request
that semaphore’s status or remove its request for that semaphore to perform
another task and occasionally attempt again to gain control of the token via
the set and test sequence. Once the right side has relinquished the token,
the left side should succeed in gaining control.
The semaphore flags are active LOW. A token is requested by writing
Figure 3. Busy and chip enable routing for both width and depth
expansion with IDT7007 RAMs.
When expanding an IDT7007 RAM array in width while using BUSY
logic, one master part is used to decide which side of the RAMs array will
receive a BUSY indication, and to output that indication. Any number of
slaves to be addressed in the same address range as the master, use the
BUSY signal as a write inhibit signal. Thus on the IDT7007 RAM the BUSY
pin is an output if the part is used as a master (M/S pin = H), and the BUSY
pin is an input if the part used as a slave (M/S pin = L) as shown in
Figure 3.
If two or more master parts were used when expanding in width, a split
decision could result with one master indicating BUSY on one side of the
array and another master indicating BUSY on one other side of the array.
This would inhibit the write operations from one port for part of a word and
inhibit the write operations from the other port for the other part of the word.
The BUSY arbitration, on a master, is based on the chip enable and
address signals only. It ignores whether an access is a read or write. In
a master/slave array, both address and chip enable must be valid long
enough for a BUSY flag to be output from the master before the actual write
pulse can be initiated with the R/W signal. Failure to observe this timing can
result in a glitched internal write inhibit signal and corrupted data in the
slave.
2940 drw 19
MASTER
Dual Port
RAM
BUSY (R)
CE
MASTER
Dual Port
RAM
BUSY (R)
SLAVE
Dual Port
RAM
BUSY (R)
SLAVE
Dual Port
RAM
BUSY (R)
BUSY (L)
BUSY (R)
D
E
C
O
D
E
R
CE
CE
CE
BUSY (L)
BUSY (L)
BUSY (L)
BUSY (L)

7007L35J

Mfr. #:
Manufacturer:
Description:
SRAM 256K(32K X 8) DUAL PORT
Lifecycle:
New from this manufacturer.
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