6.42
IDT70V9359/49L
High-Speed 3.3V 8/4K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
10
Timing Waveform with Port-to-Port Flow-Through Read
(4,5,7)
Timing Waveform of a Bank Select Pipelined Read
(1,2)
t
SC
t
HC
CE
0(B1)
ADDRESS
(B1)
A
0
A
1
A
2
A
3
A
4
A
5
t
SA
t
HA
CLK
5638 drw 09
Q
0
Q
1
Q
3
DATA
OUT(B1)
t
CH2
t
CL2
t
CYC2
(3)
ADDRESS
(B2)
A
0
A
1
A
2
A
3
A
4
A
5
t
SA
t
HA
CE
0(B2)
DATA
OUT(B2)
Q
2
Q
4
t
CD2
t
CD2
t
CKHZ
t
CD2
t
CKLZ
t
DC
t
CKHZ
t
CD2
t
CKLZ
(3)
(3)
t
SC
t
HC
(3)
t
CKHZ
(3)
t
CKLZ
(3)
t
CD2
A
6
A
6
t
DC
t
SC
t
HC
t
SC
t
HC
DATA
IN "A"
CLK
"B"
R/W
"B"
ADDRESS
"A"
R/W
"A"
CLK
"A"
ADDRESS
"B"
NO
MATCH
MATCH
NO
MATCH
MATCH
VALID
t
CWDD
t
CD1
t
DC
DATA
OUT "B"
5638 drw 10
VALID
VALID
t
SW
t
HW
t
SA
t
HA
t
SD
t
HD
t
HW
t
CD1
t
CCS
t
DC
t
SA
t
SW
t
HA
(6)
(6)
NOTES:
1. B1 Represents Bank #1; B2 Represents Bank #2. Each Bank consists of one IDT70V9359/49 for this waveform, and are setup for depth expansion in this
example. ADDRESS
(B1) = ADDRESS(B2) in this situation.
2. UB, LB, OE, and ADS = V
IL; CE1(B1), CE1(B2), R/W and CNTRST = VIH.
3. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
4. CE
0, UB, LB, and ADS = VIL; CE1 and CNTRST = VIH.
5. OE = V
IL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.
6. If t
CCS < maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD.
If t
CCS > maximum specified, then data from right port READ is not valid until tCCS + tCD1. tCWDD does not apply in this case.
7. All timing is the same for both Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite from Port "A".
