6.42
IDT70V9359/49L
High-Speed 3.3V 8/4K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
4
NOTES:
1. "H" = V
IH, "L" = VIL, "X" = Don't Care.
2. ADS, CNTEN, CNTRST = X.
3. OE is an asynchronous input signal.
Truth Table I—Read/Write and Enable Control
(1,2,3)
Pin Names
Left Port Right Port Names
CE
0L,
CE
1L
CE
0R,
CE
1R
Chip Enables
(3)
R/W
L
R/W
R
Read/Write Enable
OE
L
OE
R
Output Enable
A
0L
- A
12L
(1)
A
0R
- A
12R
(1 )
Address
I/O
0L
- I/O
17L
I/O
0R
- I/O
17R
Data Input/Output
CLK
L
CLK
R
Clock
UB
L
UB
R
Upper Byte Select
(2 )
LB
L
LB
R
Lower Byte Select
(2 )
ADS
L
ADS
R
Address Strobe Enable
CNTEN
L
CNTEN
R
Counter Enable
CNTRST
L
CNTRST
R
Counter Reset
FT/PIPE
L
FT/PIPE
R
Flow-Through / Pipeline
V
DD
Power (3.3V)
V
SS
Ground (0V)
5638 tbl 01
OE
CLK
CE
0
(5)
CE
1
(5)
UB
(4)
LB
(4)
R/W
Upper Byte
I/O
9-1 7
Lower Byte
I/O
0-8
MODE
X
H X X X X High-Z High-Z Deselected–Power Down
X
X L X X X High-Z High-Z Deselected–Power Down
X
L H H H X High-Z High-Z Both Bytes Deselected
X
LHLHL DATA
IN
High-Z Write to Upper Byte Only
X
LHHLL High-Z DATA
IN
Write to Lower Byte Only
X
LHLLL DATA
IN
DATA
IN
Write to Both Bytes
L
LHLHH DATA
OUT
High-Z Read Upper Byte Only
L
LHHLH High-Z DATA
OUT
Read Lower Byte Only
L
LHLLH DATA
OUT
DATA
OUT
Read Both Bytes
H X L H X X X High-Z High-Z Outputs Disabled
5638 tbl 02
NOTE:
1. A
12 is a NC for IDT70V9349.
2. LB and UB are single buffered regardless of state of FT/PIPE.
3. CEo and CE
1 are single buffered when FT/PIPE = VIL,
CEo and CE
1 are double buffered when FT/PIPE = VIH,
i.e. the signals take two cycles to deselect.
4 LB and UB are single buffered regardless of state of FT/PIPE.
5. CEo and CE
1 are single buffered when FT/PIPE = VIL. CEo and CE1 are double buffered when FT/PIPE = VIH, i.e. the signals take two cycles to deselect.
6.42
IDT70V9359/49L
High-Speed 3.3V 8/4K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
5
Recommended Operating
Temperature and Supply Voltage
Recommended DC Operating
Conditions
Absolute Maximum Ratings
(1)
NOTES:
1. These parameters are determined by device characterization, but are not
production tested.
2. 3dV references the interpolated capacitance when the input and output switch
from 0V to 3V or from 3V to 0V.
3. C
OUT also references CI/O.
Capacitance
(1)
(TA = +25°C, f = 1.0MHZ)
Truth Table II—Address Counter Control
(1,2)
NOTES:
1. V
IL > -1.5V for pulse width less than 10 ns.
2. V
TERM must not exceed VDD+0.3V.
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. V
TERM must not exceed VDD +0.3V for more than 25% of the cycle time or 10ns
maximum, and is limited to
< 20mA for the period of VTERM > VDD + 0.3V.
NOTES:
1. This is the parameter T
A. This is the "instant on" case temperature.
External
Address
Previous
Internal
Address
Internal
Address
Used CLK
ADS CNTEN CNTRST
I/O
(3 )
MODE
An X An
L
(4 )
XHD
I/O
(n) External Address Used
XAnAn + 1
H L
(5)
HD
I/O
(n+1) Counter Enabled—Internal Address generation
X An + 1 An + 1
HH HD
I/O
(n+1) External Address Blocked—Counter disabled (An + 1 reused)
XXA
0
XX L
(4 )
D
I/O
(0) Counter Reset to Address 0
5638 tbl 03
Grade
Ambient
Temperature
(1 )
GND V
DD
Commercial 0
O
C to +70
O
C0V3.3V
+
0.3V
Industrial -40
O
C to +85
O
C0V 3.3V
+
0.3V
5638 tbl 04
Symbol Parameter Min. Typ. Max. Unit
V
DD
Supply Voltage 3.0 3.3 3.6 V
V
SS
Ground 0 0 0 V
V
IH
Input High Voltage 2.0
____
V
DD
+0.3V
(2 )
V
V
IL
Input Low Voltage -0.3
(1 )
____
0.8 V
5638 tbl 05
Symbol Rating Commercial
& Industrial
Unit
V
TE R M
(2)
Terminal Voltage
with Respect to
GND
-0.5 to +4.6 V
T
BIAS
Tem p e r atu r e
Under Bias
-55 to +125
o
C
T
STG
Storage
Tem p e r atu r e
-65 to +150
o
C
I
OUT
DC Output Current 50 mA
56 38 tbl 06
Symbol Parameter Conditions
(2 )
Max. Unit
C
IN
Input Capacitance V
IN
= 3dV 9 pF
C
OUT
(3)
Output Capacitance V
OUT
= 3dV 10 pF
5638 tbl 07
NOTES:
1. "H" = V
IH, "L" = VIL, "X" = Don't Care.
2. CE
0, LB, UB, and OE = VIL; CE1 and R/W = VIH.
3. Outputs configured in Flow-Through Output mode: if outputs are in Pipelined mode the data out will be delayed by one cycle.
4. ADS and CNTRST are independent of all other signals including CE
0, CE1, UB and LB.
5. The address counter advances if CNTEN = V
IL on the rising edge of CLK, regardless of all other signals including CE0, CE1, UB and LB.
6.42
IDT70V9359/49L
High-Speed 3.3V 8/4K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
6
DC Electrical Characteristics Over the Operating
Temperature Supply Voltage Range
(3)
(VDD = 3.3V ± 0.3V)
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
( VDD= 3.3V ± 0.3V)
NOTE:
1. At V
DD < 2.0V input leakages are undefined.
NOTES:
1. At f = f
MAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input
levels of GND to 3V.
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. V
DD = 3.3V, TA = 25°C for Typ, and are not production tested. ICC DC(f=0) = 90mA (Typ).
5. CE
X = VIL means CE0X = VIL and CE1X = VIH
CEX = VIH means CE0X = VIH or CE1X = VIL
CEX < 0.2V means CE0X < 0.2V and CE1X > VDD - 0.2V
CE
X > VDD - 0.2V means CE0X > VDD - 0.2V or CE1X < 0.2V
"X" represents "L" for left port or "R" for right port.
Symbol Parameter Test Conditions
70V9359/49L
UnitMin. Max.
|I
LI
| Input Leakage Current
(1)
V
DD
= 3.6V, V
IN
= 0V t
o
V
DD
___
A
|I
LO
| Output Leakage Current
CE = V
IH
or CE
1
= V
IL
, V
OUT
= 0V t
o
V
DD
___
A
V
OL
Output Low Voltage I
OL
= +4mA
___
0.4 V
V
OH
Output High Voltage I
OH
= -4mA 2.4
___
V
5638 tbl 08
70V9359/49L6
Com'l Only
70V9359/49L7
Com'l & Ind
70V9359/49L9
Com'l Only
Symbol Parameter Test Condition Version Typ.
(4)
Max. Typ.
(4 )
Max. Typ.
(4 )
Max. Unit
I
DD
Dynamic Operating
Current (Both
Ports Active)
CE
L
and CE
R
= V
IL
,
Outputs Disabled,
f = f
MAX
(1 )
COM'L L 175 330 155 280 135 230
mA
IND L
____ ____
155 330
____ ____
I
SB1
Standby Current
(Both Ports - TTL
Level Inputs)
CE
L
= CE
R
= V
IH
f = f
MAX
(1 )
COM'L L 50 80 40 70 30 60
mA
IND L
____ ____
40 80
____ ____
I
SB2
Standby
Current (One
Port - TTL
Level Inputs)
CE
"A"
= V
IL
and
CE
"B"
= V
IH
(5 )
Active Port Outputs
Disabled, f=f
MAX
(1 )
COM'L L 115 185 105 170 95 155
mA
IND L
____ ____
105 180
____ ____
I
SB3
Full Standby
Current (Both
Ports - CMOS
Level Inputs)
Both Ports CE
L
and
CE
R
>V
DD
- 0.2V,
V
IN
> V
DD
- 0.2V or
V
IN
< 0.2V, f = 0
(2 )
COM'L L 0.5 3.0 0.5 3.0 0.5 3.0
mA
IND L
____ ____
0.5 3.0
____ ____
I
SB4
Full Standby
Current (One
Port - CMOS
Level Inputs)
CE
"A"
< 0.2V and
CE
"B"
> V
DD
- 0.2V
(5)
V
IN
> V
DD
- 0.2V or
V
IN
< 0.2V, Active Port,
Outputs Disabled, f = f
MAX
(1 )
COM'L L 105 175 95 160 85 145
mA
IND L
____ ____
95 175
____ ____
5638 tbl 09

70V9359L7PF8

Mfr. #:
Manufacturer:
IDT
Description:
SRAM 8K X 18 SYNC DP SRAM
Lifecycle:
New from this manufacturer.
Delivery:
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