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70V9359L7PF8

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
6.42
IDT70V9359/49L
High-Speed 3.3V 8/4K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
13
Timing Waveform of Pipelined Read with Address Counter Advance
(1)
Timing Waveform of Flow-Through Read with Address Counter Advance
(1)
NOTES:
1. CE
0, OE, UB, and LB = VIL; CE1, R/W, and CNTRST = VIH.
2. If there is no address change via ADS = V
IL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then the data
output remains constant for subsequent clocks.
ADDRESS
An
CLK
DATA
OUT
Qx - 1
(2)
Qx
Qn
Qn + 2
(2)
Qn + 3
ADS
CNTEN
t
CYC2
t
CH2
t
CL2
5638 drw 15
t
SA
t
HA
t
SAD
t
HAD
t
CD2
t
DC
READ
EXTERNAL
ADDRESS
READ WITH COUNTER
COUNTER
HOLD
t
SAD
t
HAD
t
SCN
t
HCN
READ
WITH
COUNTER
Qn + 1
ADDRESS
An
CLK
DATA
OUT
Qx
(2)
Qn
Qn + 1 Qn + 2
Qn + 3
(2)
Qn + 4
ADS
CNTEN
t
CYC1
t
CH1
t
CL1
5638 drw 16
t
SA
t
HA
t
SAD
t
HAD
READ
EXTERNAL
ADDRESS
READ WITH COUNTER COUNTER
HOLD
t
CD1
t
DC
t
SAD
t
HAD
t
SCN
t
HCN
READ
WITH
COUNTER
6.42
IDT70V9359/49L
High-Speed 3.3V 8/4K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
14
ADDRESS
(4)
An
D
0
t
CH2
t
CL2
t
CYC2
Q
0
Q
1
0
CLK
DATA
IN
R/
W
CNTRST
5638 drw 18
INTERNAL
(3)
ADDRESS
ADS
CNTEN
t
SRST
t
HRST
t
SD
t
HD
t
SW
t
HW
COUNTER
RESET
WRITE
ADDRESS 0
READ
ADDRESS 0
READ
ADDRESS 1
READ
ADDRESS n
Qn
An + 1
An + 2
READ
ADDRESS n+1
DATA
OUT
(5)
t
SA
t
HA
1 An An + 1
(6)
Ax
t
SAD
t
HAD
t
SCN
t
HCN
(6)
Timing Waveform of Write with Address Counter Advance
(Flow-Through or Pipelined Outputs)
(1)
Timing Waveform of Counter Reset (Pipelined Outputs)
(2)
ADDRESS
An
CLK
DATA
IN
Dn
Dn + 1
Dn + 1 Dn + 2
ADS
CNTEN
(7)
t
CH2
t
CL2
t
CYC2
5638 drw 17
INTERNAL
(3)
ADDRESS
An
(7)
An + 1
An + 2
An + 3
An + 4
Dn + 3
Dn + 4
t
SA
t
HA
t
SAD
t
HAD
WRITE
COUNTER HOLD
WRITE WITH COUNTER
WRITE
EXTERNAL
ADDRESS
WRITE
WITH COUNTER
t
SD
t
HD
NOTES:
1. CE
0, UB, LB, and R/W = VIL; CE1 and CNTRST = VIH.
2.
CE
0, UB, LB = VIL; CE1 = VIH.
3. The "Internal Address" is equal to the "External Address" when ADS = V
IL and equals the counter output when ADS = VIH.
4. Addresses do not have to be accessed sequentially since ADS = V
IL constantly loads the address on the rising edge of the CLK; numbers are for reference use only.
5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
6. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset cycle. ADDR
0 will be accessed. Extra cycles
are shown here simply for clarification.
7. CNTEN = V
IL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance.
The ‘An +1’ Address is written to during this cycle.
6.42
IDT70V9359/49L
High-Speed 3.3V 8/4K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
15
Depth and Width Expansion
The IDT70V9359/49 features dual chip enables (refer to Truth Table
I) in order to facilitate rapid and simple depth expansion with no require-
ments for external logic. Figure 4 illustrates how to control the varioius chip
enables in order to expand two devices in depth.
The IDT70V9359/49 can also be used in applications requiring
expanded width, as indicated in Figure 4. Since the banks are allocated
at the discretion of the user, the external controller can be set up to drive
the input signals for the various devices as required to allow for 36-bit or
wider applications.
5638 drw 19
IDT70V9359/49
CE
0
CE
1
CE
1
CE
0
CE
0
CE
1
A
13
/A
12
(1)
CE
1
CE
0
V
DD
V
DD
IDT70V9359/49
IDT70V9359/49
IDT70V9359/49
Control Inputs
Control Inputs
Control Inputs
Control Inputs
CNTRS
T
CLK
ADS
CNTEN
R/W
LB, UB
OE
Figure 4. Depth and Width Expansion with IDT70V9359/49
Functional Description
The IDT70V9359/49 provides a true synchronous Dual-Port Static
RAM interface. Registered inputs provide minimal set-up and hold times
on address, data, and all critical control inputs. All internal registers are
clocked on the rising edge of the clock signal, however, the self-timed
internal write pulse is independent of the LOW to HIGH transition of the clock
signal.
An asynchronous output enable is provided to ease asynchronous
bus interfacing. Counter enable inputs are also provided to stall the
operation of the address counters for fast interleaved memory applications.
CE0 = VIL and CE1 = VIH for one clock cycle will power down the
internal circuitry to reduce static power consumption. Multiple chip enables
allow easier banking of multiple IDT70V9359/49's for depth expansion
configurations. When the Pipelined output mode is enabled, two cycles are
required with CE0 = VIL and CE1 = VIH to re-activate the outputs.
NOTE:
1. A
13 is for IDT70V9359, A12 is for IDT70V9349.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

70V9359L7PF8

Mfr. #:
Buy 70V9359L7PF8
Manufacturer:
IDT
Description:
SRAM 8K X 18 SYNC DP SRAM
Lifecycle:
New from this manufacturer.
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