9ZX21501B
FIFTEEN OUTPUT DIFFERENTIAL ZBUFFER FOR PCIE GEN2/3 AND QPI
IDT®
FIFTEEN OUTPUT DIFFERENTIAL ZBUFFER FOR PCIE GEN2/3 AND QPI 3
9ZX21501B REV E 041613
Pin Descriptions
PIN #
PIN NAME TYPE DESCRIPTION
1IREF OUT
This pin establishes the reference for the differential current-mode output pairs. It requires a fixed precision
resistor to ground. 475ohm is the standard value for 100ohm differential impedance. Other impedances
require different values. See data sheet.
2 100M_133M# IN
3.3V Input to select operating frequency
See Functionality Table for Definition
3 HIBW_BYPM_LOBW# IN
Trilevel input to select High BW, Bypass or Low BW mode.
See PLL Operating Mode Table for Details.
4 CKPWRGD_PD# IN
Notifies device to sample latched inputs and start up on first high assertion, or exit Power Down Mode on
subsequent assertions. Low enters Power Down Mode.
5 GND PWR Ground pin.
6 VDDR PWR
3.3V power for differential input clock (receiver). This VDD should be treated as an analog power rail and
filtered appropriately.
7 DIF_IN IN 0.7 V Differential TRUE input
8 DIF_IN# IN 0.7 V Differential Complementary Input
9 SMB_A0_tri IN
SMBus address bit. This is a tri-level input that works in conjunction with the SMB_A1 to decode 1 of 9
SMBus Addresses.
10 SMBDAT I/O Data pin of SMBUS circuitry, 5V tolerant
11 SMBCLK IN Clock pin of SMBUS circuitry, 5V tolerant
12 SMB_A1_tri IN
SMBus address bit. This is a tri-level input that works in conjunction with the SMB_A0 to decode 1 of 9
SMBus Addresses.
13 DFB_IN IN
True half of differential feedback input, provides feedback signal to the PLL for synchronization with the
input clock to elimate phase error.
Complementary half of differential feedback input, provides feedback signal to the PLL for synchronization
with input clock to elimate phase error.
15 DFB_OUT# OUT
Complementary half of differential feedback output, provides feedback signal to the PLL for
synchronization with input clock to eliminate phase error.
16 DFB_OUT OUT
True half of differential feedback output, provides feedback signal to the PLL for synchronization with the
input clock to eliminate phase error.
17 DIF_0 OUT 0.7V differential true clock output
18 DIF_0# OUT 0.7V differential Complementary clock output
19 VDD PWR Power supply, nominal 3.3V
20 DIF_1 OUT 0.7V differential true clock output
21 DIF_1# OUT 0.7V differential Complementary clock output
22 DIF_2 OUT 0.7V differential true clock output
23 DIF_2# OUT 0.7V differential Complementary clock output
24 GND PWR Ground pin.
25 DIF_4 OUT 0.7V differential true clock output
26 DIF_4# OUT 0.7V differential Complementary clock output
27 VDD PWR Power supply, nominal 3.3V
28 DIF_5 OUT 0.7V differential true clock output
29 DIF_5# OUT 0.7V differential Complementary clock output
30 OE5# IN
Active low input for enabling DIF pair 5.
1 =disable outputs, 0 = enable outputs
31 DIF_6 OUT 0.7V differential true clock output
32 DIF_6# OUT 0.7V differential Complementary clock output
33 OE6# IN
Active low input for enabling DIF pair 6.
1 =disable outputs, 0 = enable outputs
34 DIF_7 OUT 0.7V differential true clock output
35 DIF_7# OUT 0.7V differential Complementary clock output
36 OE7# IN
Active low input for enabling DIF pair 7.
1 =disable outputs, 0 = enable outputs
