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9ZX21501BKLF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
9ZX21501B
FIFTEEN OUTPUT DIFFERENTIAL ZBUFFER FOR PCIE GEN2/3 AND QPI
IDT®
FIFTEEN OUTPUT DIFFERENTIAL ZBUFFER FOR PCIE GEN2/3 AND QPI 4
9ZX21501B REV E 041613
Pin Descriptions (continued)
37 DIF_8 OUT 0.7V differential true clock output
38 DIF_8# OUT 0.7V differential Complementary clock output
39 OE8# IN
Active low input for enabling DIF pair 8.
1 =disable outputs, 0 = enable outputs
40 GND PWR Ground pin.
41 VDD PWR Power supply, nominal 3.3V
42 NC N/A No Connection.
43 DIF_10 OUT 0.7V differential true clock output
44 DIF_10# OUT 0.7V differential Complementary clock output
45 OE10# IN
Active low input for enabling DIF pair 10.
1 =disable outputs, 0 = enable outputs
46 DIF_11 OUT 0.7V differential true clock output
47 DIF_11# OUT 0.7V differential Complementary clock output
48 OE11# IN
Active low input for enabling DIF pair 11.
1 =disable outputs, 0 = enable outputs
49 DIF_12 OUT 0.7V differential true clock output
50 DIF_12# OUT 0.7V differential Complementary clock output
51 OE12# IN
Active low input for enabling DIF pair 12.
1 =disable outputs, 0 = enable outputs
52 VDD PWR Power supply, nominal 3.3V
53 DIF_13 OUT 0.7V differential true clock output
54 DIF_13# OUT 0.7V differential Complementary clock output
55 GND PWR Ground pin.
56 DIF_15 OUT 0.7V differential true clock output
57 DIF_15# OUT 0.7V differential Complementary clock output
58 DIF_16 OUT 0.7V differential true clock output
59 DIF_16# OUT 0.7V differential Complementary clock output
60 VDD PWR Power supply, nominal 3.3V
61 DIF_17 OUT 0.7V differential true clock output
62 DIF_17# OUT 0.7V differential Complementary clock output
63 VDDA PWR 3.3V power for the PLL core.
64 GNDA PWR Ground pin for the PLL core.
9ZX21501B
FIFTEEN OUTPUT DIFFERENTIAL ZBUFFER FOR PCIE GEN2/3 AND QPI
IDT®
FIFTEEN OUTPUT DIFFERENTIAL ZBUFFER FOR PCIE GEN2/3 AND QPI 5
9ZX21501B REV E 041613
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 9ZX21501B. These ratings, which are standard
values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over
the recommended operating temperature range.
Electrical Characteristics–Clock Input Parameters
PARAMETER SYMBOL CONDITIONS
MIN TYP MAX
UNITS NOTES
3.3V Core Supply Voltage VDDA 4.6 V 1,2
3.3V Logic Supply Voltage VDD 4.6 V
1,2
Input Low Voltage V
IL
GND-0.5 V 1
Input High Voltage V
IH
Except for SMBus interface V
DD
+0.5V V 1
Input High Voltage V
IHSMB
SMBus clock and data pins 5.5V V 1
Storage Temperature Ts -65 150
°
C
1
Junction Temperature Tj 125 °C
1
Input ESD protection
ESD prot Human Body Model 2000 V 1
1
Guaranteed by design and characterization, not 100% tested in production.
2
Operation under these conditions is neither implied nor
g
uaranteed.
TA = T
COM;
Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Input High Voltage - DIF_IN V
IHDI F
Differential inputs
(sin
g
le-ended measurement)
600 750 1150 mV 1
Input Low Voltage - DIF_IN V
ILDIF
Differential inputs
(single-ended measurement)
V
SS
- 300 0 300 mV 1
Input Common Mode
Volta
g
e - DIF_IN
V
COM
Common Mode Input Voltage 300 1000 mV 1
Input Amplitude - DIF_IN V
SWING
Peak to Peak value 300 1450 mV 1
Input Slew Rate - DIF_IN dv/dt Measured differentially 0.4 8 V/ns 1,2
Input Leakage Current I
IN
V
IN
= V
DD ,
V
IN
= GND -5 5 uA 1
Input Duty Cycle d
tin
Measurement from differential wavefrom 45 55 % 1
Input Jitter - Cycle to Cycle J
DIFI n
Differential Measurement 0 125 ps 1
1
Guaranteed by design and characterization, not 100% tested in production.
2
Slew rate measured throu
g
h +/-75mV window centered around differential zero
9ZX21501B
FIFTEEN OUTPUT DIFFERENTIAL ZBUFFER FOR PCIE GEN2/3 AND QPI
IDT®
FIFTEEN OUTPUT DIFFERENTIAL ZBUFFER FOR PCIE GEN2/3 AND QPI 6
9ZX21501B REV E 041613
Electrical Characteristics–Input/Supply/Common Output Parameters
TA = T
COM;
Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Ambient Operating
Temperature
T
COM
Commmercial range 0 70 °C 1
Input High Voltage V
IH
Single-ended inputs, except SMBus, low
threshold and tri-level inputs
2V
DD
+ 0.3 V 1
Input Low Voltage V
IL
Single-ended inputs, except SMBus, low
threshold and tri-level inputs
GND
- 0.3 0.8 V 1
I
IN
Single-ended inputs, V
IN
= GND, V
IN
= VDD -5 5 uA 1
I
INP
Single-ended inputs
V
IN
= 0 V; Inputs with internal pull-up resistors
V
IN
= VDD; Inputs with internal pull-down resistors
-200 200 uA 1
F
ib
yp
V
DD
= 3.3 V, Bypass mode 33 400 MHz 2
F
i
p
ll
V
DD
= 3.3 V, 100MHz PLL mode 90 100.00 105 MHz 2
F
i
p
ll
V
DD
= 3.3 V, 133.33MHz PLL mode 120 133.33 140 MHz 2
Pin Inductance L
p
in
7nH1
C
IN
Logic Inputs, except DIF_IN 1.5 5 pF 1
C
INDIF_IN
DIF_IN differential clock inputs 1.5 2.7 pF 1,4
C
OUT
Output pin capacitance 6 pF 1
Clk Stabilization T
STAB
From V
DD
Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
1.8 ms 1,2
Input SS Modulation
Frequency
f
MODI N
Allowable Frequency
(Trian
g
ular Modulation)
30 33 kHz 1
OE# Latency t
LATOE#
DIF start after OE# assertion
DIF stop after OE# deassertion
412clocks1,3
Tdrive_PD# t
DRVPD
DIF output enable after
PD# de-assertion
300 us 1,3
Tfall t
F
Fall time of control inputs 5 ns 1,2
Trise t
R
Rise time of control inputs 5 ns 1,2
SMBus Input Low Voltage V
ILSMB
0.8 V 1
SMBus Input High Voltage V
IHSMB
2.1 V
DDSMB
V1
SMBus Output Low Voltage V
OLSMB
@ I
PULLUP
0.4 V 1
SMBus Sink Current I
PULLUP
@ V
OL
4mA1
Nominal Bus Voltage V
DDSMB
3V to 5V +/- 10% 2.7 5.5 V 1
SCLK/SDATA Rise Time t
RSMB
(Max VIL - 0.15) to (Min VIH + 0.15) 1000 ns 1
SCLK/SDATA Fall Time t
FSMB
(Min VIH + 0.15) to (Max VIL - 0.15) 300 ns 1
SMBus Operating
Frequency
f
MAXSMB
Maximum SMBus operating frequency 100 kHz 1,5
1
Guaranteed by desi
g
n and characterization, not 100% tested in production.
2
Control input must be monotonic from 20% to 80% of input swin
g
.
5
The differential input clock must be running for the SMBus to be active
Input Current
3
Time from deassertion until out
p
uts are >200 mV
4
DIF_IN input
Capacitance
Input Frequency
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

9ZX21501BKLF

Mfr. #:
Buy 9ZX21501BKLF
Manufacturer:
IDT
Description:
Clock Buffer PCIE BUFFER - Z TECH
Lifecycle:
New from this manufacturer.
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