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74ABT374APW,118

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
74ABT374A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 18 December 2012 4 of 16
NXP Semiconductors
74ABT374A
Octal D-type flip-flop; positive-edge trigger; 3-state
7. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 C.
8. Recommended operating conditions
9. Static characteristics
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V
CC
supply voltage 0.5 +7.0 V
V
I
input voltage
[1]
1.2 +7.0 V
V
O
output voltage output in OFF-state or HIGH-state
[1]
0.5 +5.5 V
I
IK
input clamping current V
I
< 0 V 18 - mA
I
OK
output clamping current V
O
< 0 V 50 - mA
I
O
output current output in LOW-state - 128 mA
T
j
junction temperature
[2]
- 150 C
T
stg
storage temperature 65 +150 C
Table 5. Operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
V
CC
supply voltage 4.5 - 5.5 V
V
I
input voltage 0 - V
CC
V
V
IH
HIGH-level input voltage 2.0 - - V
V
IL
LOW-level input voltage - - 0.8 V
I
OH
HIGH-level output current 32--mA
I
OL
LOW-level output current - - 64 mA
t/V input transition rise and fall rate 0 - 10 ns/V
T
amb
ambient temperature in free air 40 - +85 C
Table 6. Static characteristics
Symbol Parameter Conditions 25 C 40 C to +85 C Unit
Min Typ Max Min Max
V
IK
input clamping voltage V
CC
= 4.5 V; I
IK
= 18 mA 1.2 0.9 - 1.2 - V
V
OH
HIGH-level output
voltage
V
I
= V
IL
or V
IH
V
CC
= 4.5 V; I
OH
= 3 mA 2.5 2.9 - 2.5 - V
V
CC
= 5.0 V; I
OH
= 3 mA 3.0 3.4 - 3.0 - V
V
CC
= 4.5 V; I
OH
= 32 mA 2.0 2.4 - 2.0 - V
V
OL
LOW-level output
voltage
V
CC
= 4.5 V; I
OL
=64mA;
V
I
=V
IL
or V
IH
- 0.42 0.55 - 0.55 V
74ABT374A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 18 December 2012 5 of 16
NXP Semiconductors
74ABT374A
Octal D-type flip-flop; positive-edge trigger; 3-state
[1] For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
[2] This parameter is valid for any V
CC
between 0 V and 2.1 V, with a transition time of up to 10 ms. From V
CC
= 2.1 V to V
CC
= 5 V 10 %
a transition time of up to 100 s is permitted.
[3] Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
[4] This is the increase in supply current for each input at 3.4 V.
10. Dynamic characteristics
V
OL(pu)
power-up LOW-level
output voltage
V
CC
= 5.5 V; I
O
=1mA;
V
I
=GNDor V
CC
[1]
- 0.13 0.55 - 0.55 V
I
I
input leakage current V
CC
=5.5V; V
I
=V
CC
or GND - 0.01 1.0 - 1.0 A
I
OFF
power-off leakage
current
V
CC
= 0 V; V
I
or V
O
4.5 V - 5.0 100 - 100 A
I
O(pu/pd)
power-up/power-down
output current
V
CC
=2.0V; V
O
=0.5V;
V
I
=GNDor V
CC
; OE HIGH
[2]
- 5.0 50 - 50 A
I
OZ
OFF-state output
current
V
CC
= 5.5 V; V
I
= V
IL
or V
IH
V
O
= 2.7 V - 5.0 50 - 50 A
V
O
= 0.5 V 50 5.0 - 50 - A
I
LO
output leakage current HIGH-state; V
O
=5.5V;
V
CC
=5.5V; V
I
=GNDor V
CC
-5.050 - 50A
I
O
output current V
CC
= 5.5 V; V
O
= 2.5 V
[3]
180 100 50 180 50 mA
I
CC
supply current V
CC
= 5.5 V; V
I
= GND or V
CC
outputs HIGH-state - 110 250 - 250 A
outputs LOW-state - 24 30 - 30 mA
outputs disabled - 110 250 - 250 A
I
CC
additional supply
current
per input pin; V
CC
= 5.5 V;
one input at 3.4 V;
other inputs at V
CC
or GND
[4]
-0.51.5 - 1.5mA
C
I
input capacitance V
I
=0Vor V
CC
-4- - -pF
C
O
output capacitance outputs disabled; V
O
=0Vor V
CC
-7- - -pF
Table 6. Static characteristics …continued
Symbol Parameter Conditions 25 C 40 C to +85 C Unit
Min Typ Max Min Max
Table 7. Dynamic characteristics
GND = 0 V; for test circuit, see Figure 9
.
Symbol Parameter Conditions 25 C; V
CC
= 5.0 V 40 C to +85 C;
V
CC
= 5.0 V 0.5 V
Unit
Min Typ Max Min Max
f
max
maximum
frequency
see Figure 6 200 300 - 200 - MHz
t
PLH
LOW to HIGH
propagation delay
CP to Qn; see Figure 6 1.7 3.4 4.5 1.7 5.1 ns
t
PHL
HIGH to LOW
propagation delay
CP to Qn; see Figure 6 2.0 3.8 4.9 2.0 5.2 ns
t
PZH
OFF-state to HIGH
propagation delay
OE to Qn; see Figure 8 1.2 3.5 4.5 1.2 5.4 ns
74ABT374A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 18 December 2012 6 of 16
NXP Semiconductors
74ABT374A
Octal D-type flip-flop; positive-edge trigger; 3-state
11. Waveforms
t
PZL
OFF-state to LOW
propagation delay
OE to Qn; see Figure 8 2.2 4.3 5.4 2.2 6.2 ns
t
PHZ
HIGH to OFF-state
propagation delay
OE to Qn; see Figure 8 1.8 3.6 4.7 1.8 5.2 ns
t
PLZ
LOW to OFF-state
propagation delay
OE to Qn; see Figure 8 1.5 3.0 4.1 1.5 4.3 ns
t
su(H)
set-up time HIGH Dn to CP; see Figure 7 1.5 0.6 - 1.5 - ns
t
su(L)
set-up time LOW Dn to CP; see Figure 7 1.2 0.3 - 1.2 - ns
t
h(H)
hold time HIGH CP to Dn; see Figure 7 1.0 0.3 - 1.0 - ns
t
h(L)
hold time LOW CP to Dn; see Figure 7 1.0 0.5 - 1.0 - ns
t
WH
pulse width HIGH CP; see Figure 6 2.0 0.8 - 2.0 - ns
t
WL
pulse width LOW CP; see Figure 6 2.8 1.0 - 2.8 - ns
Table 7. Dynamic characteristics
…continued
GND = 0 V; for test circuit, see Figure 9.
Symbol Parameter Conditions 25 C; V
CC
= 5.0 V 40 C to +85 C;
V
CC
= 5.0 V 0.5 V
Unit
Min Typ Max Min Max
V
M
= 1.5 V
V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Fig 6. Propagation delay clock input (CP) to output (Qn), clock pulse (CP) width and maximum clock (CP)
frequency
001aac445
CP
input
Qn
output
t
PHL
t
PLH
t
WH
t
WL
1 / f
max
V
M
V
OH
V
I
GND
V
OL
V
M
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74ABT374APW,118

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Buy 74ABT374APW,118
Manufacturer:
NXP Semiconductors
Description:
Flip Flops OCTAL D 3-S
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New from this manufacturer.
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