LT8471
13
8471fd
For more information www.linear.com/8471
LT8471. Comparator CUVLO detects undervoltage condi-
tions by comparing
the OV/UV pin to typical thresholds
of 1.215V (rising) and 1.18V (falling). The COVLO com-
parator detects
over
voltage conditions by comparing the
OV/UV pin current to typical thresholds of 80μA (rising)
and 75μA (falling).
Possible reasons to use the UVLO and/or OVLO functions
are as follows: A switching regulator draws constant power
from the source, so source current increases as source
voltage drops. This looks like a negative resistance load
to the source and can cause the source to current-limit
or latch up under low source voltage conditions. UVLO
prevents the regulator from operating at source voltages
where these problems might occur. The OVLO function
is used to stop the switching regulator(s) in cases where
the input supply voltage overshoots higher than desired.
As an example, V
IN1
overvoltage and undervoltage thresh-
olds can be set independently by properly choosing R
3A
and R
3B
. Use the following formulas to determine the
resistor values:
R
3A
=
V
OVLO
+
80µA
1.37 V
UVLO
1.18 80µA
R
3B
=
1.18
V
UVLO
1.18
R
3A
where:
V
OVLO
+
is the desired rising OVLO threshold
V
UVLO
is the desired falling UVLO threshold
After R
3A
and R
3B
have been selected, the UVLO and OVLO
rising and falling thresholds can be determined using:
V
OVLO
+
= 1.37
R
3A
+ R
3B
R
3B
+ 80µA R
3A
V
OVLO
= 1.37
R
3A
+ R
3B
R
3B
+ 75µA R
3A
V
UVLO
+
= 1.215
R
3A
+ R
3B
R
3B
V
UVLO
= 1.18
R
3A
+ R
3B
R
3B
where:
V
OVLO
+
and V
OVLO
are the rising and falling OVLO
thresholds, respectively.
V
UVLO
+
and V
UVLO
are the rising and falling UVLO
thresholds, respectively.
There
are a few limitations in selecting the OVLO and UVLO
threshold voltages.
1. The UVLO threshold must be at least 2.6V so that it’s
higher than the minimum operating voltage the input
supply. If the UVLO function is not needed, R
3B
can be
omitted and R
3A
can be calculated using:
R
3A
=
V
OVLO
+
1.37V
80µA
2. The following relationship must be satisfied:
V
OVLO
+
V
UVLO
>
1.37
1.18
= 1.16
1
As the ratio of V
OVLO
to V
UVLO
gets closer to 1.161, the
required resistances for R
3A
and R
3B
become smaller,
thus increasing the operating current.
applicaTions inForMaTion
LT8471
14
8471fd
For more information www.linear.com/8471
The following example shows how to select R
3A
and R
3B
to disable the LT8471 for V
IN1
voltages below 5V and
above 15V.
First, check that the ratio of the OVLO to the UVLO thresh
-
old is greater than 1.161. Here, the ratio is 15V/5V = 3V,
which satisfies the second rule just mentioned.
Next, calculate:
R
3A
=
15V
80µA
1.37 5V
1.18 80µA
= 114.9k
Choose R
3A
to be a standard value resistance of 118k.
Next, calculate:
R
3B
=
1.18V
5V 1.18V
118k = 36.5k
Choose R
3B
to be a standard value resistance of 36.5k.
After selecting the standard value resistors for R
3A
and
R
3B
, calculate the final thresholds using the formulas
previously provided.
V
OVLO
+
= 1.37
118k
+
36.5k
36.5k
+ 80µA 118k
= 15.24V
V
OVLO
= 1.37
118k + 36.5k
36.5k
+ 75µA 118k
= 14.65V
V
UVLO
+
= 1.215
118k + 36.5k
36.5k
= 5.14V
V
UVLO
= 1.18
118k + 36.5k
36.5k
= 4.99V
Setting the Output Voltage (Primary Channels)
The output voltage is programmed with a resistor divider
between the output and the FB pin. Choose 1% or better
resistors according to:
R
A
= R
B
V
OUT
V
FB
1
where V
FB
is the feedback voltage (0.789V typical for
positive V
OUT
and –0.788V for negative V
OUT
). Reference
designators are as shown in the Block Diagram.
For example, for V
OUT
= 10V, choose R
1B
= 10k, then
choose:
R
1A
= 10k
10V
0.789V
1
115k
Start-Up Sequencing
Connecting one primary channel's PG pin to the other
channel's SS pin is an easy way to sequence the start-up
order of the outputs. For example, in most applications,
connecting PG1 to SS2 will make the channel 1 output
come up before the channel 2 output during the start-up.
Because the skyhook channel does soft-start with the
SS1 pin (see more details in the Soft-Start section), the
following guidelines need to be applied if both power-up
sequencing and the skyhook channel are used:
1. Connect PG1 directly to SS2 to make channel 1's output
come up first (see Figure 12).
2. Connect a 147k resistor between PG2 and SS1 to make
channel 2's output come up first.
An example using a 147k resistor connected between PG2
and SS1 is shown in Figure 9a. In this application, chan
-
nel 1 is configured
as a boost converter, and channel 2 is
configured as a buck converter. The buck converter has
to start up first as its output is connected to the input of
the boost converter.
applicaTions inForMaTion
LT8471
15
8471fd
For more information www.linear.com/8471
Power Switch Duty Cycle (Primary Channels)
In order to maintain loop stability and deliver adequate
current to the load, the internal power switches (Q1 and
Q2 in the Block Diagram) cannot remain on for 100% of
each clock cycle. The maximum allowable duty cycle is
given by:
DC
MAX
=
T
P
MIN
(OFF)TIME
T
P
100%
where T
P
is the clock period and MIN
(OFF)TIME
is typically
170ns (refer to the Electrical Characteristics section).
The application should be designed so that the steady state
duty cycle does not exceed DC
MAX
. Duty cycle equations
for several common topologies are given below, where V
D
is the diode forward voltage drop and V
CESAT
is typically
300mV at 1.5A.
DC
BOOST
V
OUT
– V
CC
+
V
D
V
OUT
+ V
D
V
CESAT
DC
BUCK
V
OUT
+ V
D
V
CC
+ V
D
V
CESAT
DC
1L _INV
V
OUT
+ V
D
V
CC
+ V
D
V
CESAT
+ V
OUT
DC
2L _INV
V
OUT
+ V
D
V
CC
+ V
D
V
CESAT
+ V
OUT
DC
SEPIC
V
D
+ V
OUT
V
CC
+ V
OUT
+ V
D
V
CESAT
DC
ZETA
V
D
+ V
OUT
V
CC
+ V
OUT
+ V
D
V
CESAT
where V
CC
is the positive input voltage to the DC/DC con-
verter. See the Typical Applications section for examples.
The
LT8471 can be used in configurations where the duty
cycle is higher than DC
MAX
, but it must be operated in the
discontinuous conduction mode so that the effective duty
cycle is reduced.
Inductor Selection (Primary Channels)
General Guidelines: The high frequency operation of
the LT8471 allows for the use of small surface mount
inductors. For high efficiency, choose inductors with
high frequency core material, such as ferrite, to reduce
core losses. To improve efficiency, choose inductors
with more volume for a given inductance. The inductor
should have low DCR (copper wire resistance) to reduce
I
2
R losses, and must be able to handle the peak inductor
current without saturating. Note that in some applications,
the current handling requirements of the inductor can be
lower, such as in the SEPIC topology, where each inductor
only carries a fraction of the total switch current. Molded
chokes or chip inductors usually do not have enough
core area to support peak inductor currents in the 2A to
3A range. To minimize radiated noise, use a toroidal or
shielded inductor. Note
that the
inductance of shielded
core types will drop more as current increases, and will
saturate more easily. See Table 1 for a list of inductor
manufacturers. Thorough lab evaluation is recommended
to verify that the following guidelines properly suit the
final application.
Table 1. Inductor Manufacturers
VENDOR PART NUMBER WEB
Coilcraft MSS1038, MSS7341 and
LPS4018
www.coilcraft.com
Coiltronics DR, LD and CD Series www.coiltronics.com
Sumida CDRH105R Series www.sumida.com
Würth Elektronik WE-LHMI and WE-TPC Series www.we-online.com
Minimum Inductance: Although there can be a trade-
off with efficiency, it is often desirable to minimize
board space by choosing smaller inductors. When
choosing an inductor, there are two conditions that
limit the minimum inductance; (1) providing adequate
load current, and (2) avoiding subharmonic oscillation.
Choose an inductance that is high enough to meet both
of these requirements.
applicaTions inForMaTion

LT8471EFE#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Dual Multitopology DC/DC Converters with 2.5A Switches and Synchronization
Lifecycle:
New from this manufacturer.
Delivery:
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