LT8471
24
8471fd
For more information www.linear.com/8471
Power and Thermal Calculations
Power dissipation in the LT8471 chip comes from four
primary sources: switch I
2
R losses, switch dynamic
losses, NPN base drive DC losses, and miscellaneous
input current losses. These formulas assume continuous
mode operation, so they should not be used for calculating
thermal losses or efficiency in discontinuous mode or at
light load currents.
The following example calculates the power dissipation
in the LT8471 for a particular boost application on both
CH1 and CH2 (V
IN
= 5V, V
OUT
= 12V, I
OUT
= 0.67A, f
OSC
= 1MHz, V
D
= 0.45V, V
CESAT
= 0.21V).
To calculate die junction temperature, use the appropriate
thermal resistance number and add in worst-case ambient
temperature:
T
J
= T
A
+ θ
JA
•P
TOTAL
where T
J
= Die Junction Temperature, T
A
= Ambient Tem-
perature, P
TOTAL
is the final result from the calculations
shown in Table 5, and θ
JA
is the thermal resistance from
the silicon junction to the ambient air.
The θ
JA
value is 38°C/W for the 20-lead TSSOP package
and 44°C/W for the 28-lead (4mm × 5mm) QFN package. In
practice, lower θ
JA
values can be realized if board layout is
performed with appropriate grounding (accounting for heat
sinking properties of
the board) and other considerations
listed in the Layout Guidelines section.
Thermal Lockout
A
fault condition occurs when the die temperature exceeds
164°C (see Operation Section), and the part goes into
thermal lockout. The fault condition ceases when the die
temperature drops by ~1.5°C (nominal).
V
IN
Ramp Rate
While initially powering a switching converter application,
the V
IN
ramp rate should be limited. High V
IN
ramp rates can
cause excessive inrush currents in the passive components
of the converter. This can lead to current and/or voltage
overstress and may damage the passive components or
the chip. Ramp rates less than 500mV/μs, depending on
component parameters, will generally prevent these issues.
Also, be careful to avoid hot-plugging. Hot-plugging occurs
when an active voltage supply is “instantly” connected or
switched to the input of the converter. Hot-plugging results
in very fast input ramp rates and is not recommended.
Finally, for more information, refer to Linear application
note AN88, which discusses voltage overstress that can
occur when an inductive source impedance is hot-plugged
to an input pin bypassed by ceramic capacitors.
Layout Guidelines
As with all high frequency switchers, when considering
layout, care must be taken to achieve
optimal electrical,
thermal
and noise performance. One will not get advertised
performance with a careless layout. To prevent noise, both
radiated and conducted, the high speed switching current
paths must be kept as short as possible. For each channel,
the high speed switching current flows in a loop through
the following components:
• Boost: NPN power switch (C-E pins), external Schottky
diode and output capacitor
• Buck: NPN power switch (C-E pins), external Schottky
diode and input capacitor
• 1L Inverting: NPN power switch (C-E pins), external
Schottky diode, input capacitor and output capacitor
The area inside the loop formed by these components
should be kept as small as possible. This is implemented
in the suggested layouts shown in Figure 5, Figure 6 and
Figure 7. Shortening the loop will also reduce the para
-
sitic trace
inductance. As the NPN switch turns off, the
parasitic
inductance can produce a flyback spike across
the LT8471 switch. When operating at higher currents
and output voltages, with poor layout, the spike can
generate voltages across the switch that may exceed its
absolute maximum rating. A ground plane should also
be used under the switcher circuitry to prevent interplane
coupling and overall noise. However,
there should be
no
ground plane under the planes that are connected to
applicaTions inForMaTion
