LT8471
7
8471fd
For more information www.linear.com/8471
pin FuncTions
C1, C2 (Pins 1, 20): Collector Pins. These are the collec-
tors of the primary internal NPN power switches. If either
pin
is tied to a DC voltage, it must be locally bypassed; if
either pin is a switching pin, minimize trace area connected
to the pin to minimize EMI. When the Skyhook channel is
used, the C2 pin must be tied to the input voltage of the
Skyhook channel.
C3 (Pin 13): Skyhook Collector Pin. This is the collector of
the internal NPN power switch for the Skyhook channel.
If the Skyhook channel is used, minimize the metal trace
area connected to this pin to minimize EMI. If the Skyhook
channel is not used, tie the C3 pin to GND.
E1, E2 (Pins 2, 19): Emitter Pins. These are the emit
-
ters of the primary internal NPN power switches. Unless
grounded, minimize trace area connected to these pins
to minimize EMI.
FB1, FB2 (Pins 5, 16): Feedback Pins for Primary Chan
-
nels. Connect
a resistor divider between V
OUT
, FB and
GND to set the output voltage.
GND (Pins 10, 11,12, Exposed Pad 21): Ground. All of the
ground pins must be soldered directly to the local ground
plane. The exposed pad metal of the
package provides
both
electrical contact to ground and good thermal contact to
the printed circuit board.
OV/UV (Pin 6): Overvoltage/Undervoltage Pin. Tie to 1.215V
(typical) or more to enable the device; ground to shut down.
Configurable as a UVLO and OVLO by connecting to an
external resistor divider. See the Applications Information
section for more information.
PG1, PG2 (Pins 4, 17): Power Good Pins. Connect pull-up
resistors to these pins. These open-drain output pins are
pulled low when their respective output voltages are more
than 7.5% below their target output voltages (as set by
the external feedback resistors). When the output voltage
is above 92.5% of the target voltage, the respective PG
pin driver turns off, allowing the PG voltage to rise and
indicate that the regulated output voltage is good.
RT (Pin 7): Timing Resistor Pin. Adjusts the switching
frequency. Place a resistor from this pin to ground to set
the frequency to a fixed free-running level. Do not float
this pin.
SHOUT (Pin 14): Skyhook Output Voltage Pin. This is the
cathode of the internal Schottky diode and the output of
the Skyhook boost converter.
SS1, SS2 (Pins 8, 15): Soft Start Pins. Place a soft-start
capacitor on
each pin. Upon start-up, the SS pins will be
charged by (nominally) 250k resistors to about 2.15V.
SYNC
(Pin 9): To synchronize the switching frequency
to an outside clock, simply drive this pin with a clock.
The high voltage level of the clock needs to exceed 1.3V,
and the low level should be less than 0.4V. Drive this pin
to less than 0.4V to revert to the internal free running
clock. See the Applications Information section for more
information.
V
IN1
(Pin 3): Input Supply Pin 1. This is the power supply
pin for primary channel 1 and the Skyhook channel. This
pin also provides power to additional circuitry common
to all channels. V
IN1
must be greater than 2.6V for any
channel to operate. V
IN1
must be locally bypassed.
V
IN2
(Pin 18): Input Supply Pin 2. This is the power supply
pin for primary channel 2 and must be greater than 2.6V
when channel 2 is in use. V
IN2
must be locally bypassed.
LT8471
8
8471fd
For more information www.linear.com/8471
block DiagraM
8471 BD
250k
R
Q
S
SR22
2.15V
2.15V
UVLO
OV/UVV
IN2
UVLO
C2
SHOUT
250k
R
Q
S
SR21
SOFT-
START
SOFT-
START
VC1
0.5V
DRIVER
50mV
INTERNAL
SUPPLY
REG
SYNC
BLOCK
VOLTAGE
REFS
2.15V
0.73V
0.727V
VC2
ADJUSTABLE
OSCILLATOR
FREQUENCY
FOLDBACK
RAMP
GENERATOR
OSC
OSC
–0.788V
0.789V
COMPARATOR
COMPARATOR
1.215V
+
+
+
+
+
+
SKYHOOK
DISABLE
+
Q3
Q2
C1
D1
L2
D2
DRIVER
Q1
DRIVER
C2
L1
C
SS1
R
3A
50mV
0.789V
0.789V
–0.788V
VC1
VC2
C
SS2
R
T
R
PG2
V
IN2
V
OUT2
OV/UV
LOGIC
PEAK
DETECT
Q3 SWITCH CONTROL
AND COMPENSATION
SHOUT-C2
VOLTAGE COMPARE
+
+
+
40mV 80mΩ
R
SENSE2
R
SENSE1
V
OUT1
R
2B
R
2A
R
1B
R
1A
0.5V
1.215V
1.37V
R
3B
D
SH
V
IN1
RT
FB2
PG2
GND
SYNC
V
IN1
SS2
SS1
OSC
PGOOD
DET.
PGOOD
DET.
0.73V
0.727V
FREQUENCY
FOLDBACK
–0.788V
FB1
PG1
OSC
CURRENT LIMIT
CONTROLLER
+
+
+
+
R Q
S
SR12
C3
C3
C2
E2
A42
A32
RAMP
GENERATOR
V
IN1
R Q
S
SR11
C1
E1
A41
A31
C
VCC
V
CC
L3
A43
R
PG1
LT8471
9
8471fd
For more information www.linear.com/8471
operaTion
The LT8471 consists of two primary channels, each with
a 2A power switch. One Skyhook channel is also avail-
able with
a 500mA power switch to support the primary
channels
when performing step-down conversions. The
maximum voltage between V
IN1
and E1 (or V
IN2
and E2) is
40V when E1 (or E2) is grounded. This is the case for boost,
SEPIC, flyback and dual-inductor inverting topologies. The
maximum allowed voltage between V
IN1
and E1 (or V
IN2
and E2) is 60V when E1 (or E2) is allowed to toggle, such
as in buck, ZETA and single-inductor inverting topologies.
Primary Channels
The two primary channels, 1 and 2, can be independently
configured as boost, buck, SEPIC, ZETA, flyback or invert
-
ing DC/DC converters to adapt into various applications.
Both channels use a constant-frequency, current mode
control scheme to provide line and load regulation (refer
to the Block Diagram). The channel 1 clock is in phase
with the internal oscillator or the SYNC pin if it is toggling.
In order to reduce transient switching spikes, the clock
for channel 2 is approximately 180° out-of-phase with
the channel 1 clock.
At the start of each clock phase, an
SR latch (
SR11/SR12
in the Block Diagram) is set, turning on the internal power
switch (Q1/Q2 in the Block Diagram) for the respective
channel. An amplifier (A41/A42 in the Block Diagram) and
a comparator (A31/A32 in the Block Diagram) monitor the
current flowing through the internal power switch, turning
the switch off when the current reaches a level determined
by the voltage at VC1/VC2. An error amplifier measures
the output voltage through an external resistor divider tied
to the FB1/FB2 pin and servos the VC1/VC2 voltage. If
the error amplifier’s output (VC1/VC2) increases, more
current is delivered to the output; if it decreases, less
current is delivered. An internal clamp on the VC1/VC2
voltage provides current limit.
Both of the primary channels contain a power good com
-
parator which trips when the corresponding FB pin voltage
is at 92.5% of its regulated value. The PG1 and PG2 outputs
are driven by open-drain N-channel MOSFET devices that
are off when the respective output is in regulation, allow
-
ing external resistors to pull the PG1/PG2 pins high. The
PG1
and PG2 pin states are only valid when the respective
channel is enabled and V
IN1
is above 2.6V.
Skyhook Channel
When either channel is configured as a buck, ZETA or
single-inductor inverting converter, the respective V
IN
pin(s) must be boosted above the input voltage, V
CC
. The
boosted supply provides base current to the appropriate
Q1 and/or Q2 NPN power switch. The Skyhook channel
provides this boosted voltage to the SHOUT pin which
must also be connected to V
IN2
and/or V
IN1
as needed.
The Skyhook is a constant-frequency, voltage mode
boost converter including a Schottky diode integrated on
chip. The Skyhook output, SHOUT, is regulated to a fixed
voltage (4.25V typical) above the C2 pin which must be
connected to a DC voltage (typically V
CC
). If the Skyhook is
not needed it can be disabled by tying the C3 pin to GND.
This also reduces the current draw from V
IN1
. Refer to
the Applications Information section for more information
about the proper use of the Skyhook channel.
The Skyhook operates as follows: An error amplifier mea
-
sures the output voltage (SHOUT) through the SHOUT-C2
voltage
comparator and servos an internal control volt-
age. The
control voltage determines the on-time of the
Q3
power switch for each cycle, and thus, the amount of
current being delivered to SHOUT. Loop compensation
is integrated in the chip. Comparator A43 monitors the
current in the power switch Q3 in order to detect over
current conditions. If current in excess of 500mA (typ) is
detected, switch Q3 is immediately turned off.
Start-Up Operation
Several functions are provided to enable a clean start-up
for the LT8471.
• First, the OV/UV pin voltage is monitored by an inter
-
nal voltage
reference to give a precise turn-on voltage
range.
An external resistor (or resistor divider) can be
connected from the input power supply to the OV/UV
pin to provide a user-programmable undervoltage and
overvoltage lockout function.
• Second, the soft-start circuitry provides for a gradual
ramp-up of the switch current for the primary channels

LT8471EFE#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Dual Multitopology DC/DC Converters with 2.5A Switches and Synchronization
Lifecycle:
New from this manufacturer.
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