AD8801/AD8803
REV. A
–7–
100
0.0001
2.5
0.01
0.001
0.50
0.1
1.0
10
21.51
LOGIC INPUT VOLTAGE – Volts
53 4.543.5
T
A
= +25°C
ALL DIGITAL INPUTS
TIED TOGETHER
I
DD
SUPPLY CURRENT – mA
V
DD
= +5V
V
DD
= +3V
Figure 13. Supply Current vs. Logic Input Voltage
80
60
100 100k10k1k10
40
20
FREQUENCY – Hz
PSRR – dB
0
V
DD
= +5V ±0.5V
P
V
REFH
= +2V
CODE = 80
H
T
A
= +25°C
Figure 14. Power Supply Rejection vs. Frequency
10
0%
100
90
0%
V
DD
= +5V
V
REF
= +2V
TIME – 1µs/DIV
2V
0V
5V
0V
OUT1
CS
Figure 15. Large-Signal Settling Time
Figure 16. Adjacent Channel Clock Feedthrough
10
0%
100
90
OUTPUT1: 7F
H
80
H
V
DD
= +5V
V
REF
= +2V
TIME – 0.2µs/DIV
OUT1
10mV/DIV
CS
5V/DIV
Figure 17. Midscale Transition
HOURS OF OPERATION AT 150°C
0.01
–0.01
0 600
CHANGE IN ZERO-SCALE ERROR – LSB
150 300 450
0
–0.005
0.005
V
DD
= +4.5V
V
REF
= +4.5V
SS = 162 PCS
V
REFL
= 0V
Figure 18. Zero-Scale Error Accelerated by Burn-In
REV. A
–8–
AD8801/AD8803
HOURS OF OPERATION AT 150°C
0.04
–0.04
0 600150 300 450
0
–0.02
0.02
V
DD
= +4.5V
V
REF
= +4.5V
SS = 162 PCS
x + 2σ
CHANGE IN FULL-SCALE ERROR – LSB
x
x – 2σ
Figure 19. Full-Scale Error Accelerated by Burn-In
HOURS OF OPERATION AT 150°C
1.0
INPUT RESISTANCE DRIFT – k
–1.0
0 600150 300 450
0
–0.5
0.5
V
DD
= +4.5V
V
REF
= +4.5V
CODE = 55
H
SS = 162 PCS
x + 2σ
x
x – 2σ
Figure 20. REF Input Resistance Accelerated by Burn-In
AD8801/
AD8803
V
DD
DGND
10µF
0.1µF
+
+5V
Figure 22. Recommended Supply Bypassing for the
AD8801/AD8803
Buffering the AD8801/AD8803 Output
In many cases, the nominal 5 k output impedance of the
AD8801/AD8803 is sufficient to drive succeeding circuitry. If a
lower output impedance is required, an external amplifier can
be added. Several examples are shown in Figure 23. One ampli-
fier of an OP291 is used as a simple buffer to reduce the output
resistance of DAC A. The OP291 was chosen primarily for its
rail-to-rail input and output operation, but it also offers opera-
tion to less than 3 V, low offset voltage, and low supply current.
The next two DACs, B and C, are configured in a summing ar-
rangement where DAC C provides the coarse output voltage
setting and DAC B can be used for fine adjustment. The inser-
tion of R1 in series with DAC B attenuates its contribution to
the voltage sum node at the DAC C output.
APPLICATIONS
Supply Bypassing
Precision analog products, such as the AD8801/AD8803, re-
quire a well filtered power source. Since the AD8801/AD8803
operate from a single +3 V to +5 V supply, it seems convenient
to simply tap into the digital logic power supply. Unfortunately,
the logic supply is often a switch-mode design, which generates
noise in the 20 kHz to 1 MHz range. In addition, fast logic gates
can generate glitches hundred of millivolts in amplitude due to
wiring resistances and inductances.
If possible, the AD8801/AD8803 should be powered directly
from the system power supply. This arrangement, shown in Fig-
ure 21, will isolate the analog section from the logic switching
transients. Even if a separate power supply trace is not available,
however, generous supply bypassing will reduce supply-line in-
duced errors. Local supply bypassing consisting of a 10 µF tan-
talum electrolytic in parallel with a 0.1 µF ceramic capacitor is
recommended (Figure 22).
TTL/CMOS
LOGIC
CIRCUITS
+5V
POWER SUPPLY
10µF
TANT
0.1µF
AD8801/
AD8803
+
Figure 21. Use Separate Traces to Reduce Power Supply
Noise
AD8801/AD8803
REV. A
–9–
V
H
V
L
V
H
V
L
V
H
V
L
V
REFH
V
DD
+5V
GND
V
REFL
DIGITAL INTERFACING
OMITTED FOR CLARITY
R1
100k
OP291
AD8801/
AD8803
SIMPLE BUFFER
0V TO 5V
SUMMER CIRCUIT
WITH FINE TRIM
ADJUSTMENT
Figure 23. Buffering the AD8801/AD8803 Output
Increasing Output Voltage Swing
An external amplifier can also be used to extend the output volt-
age swing beyond the power supply rails of the AD8801/AD8803.
This technique permits an easy digital interface for the DAC,
while expanding the output swing to take advantage of higher
voltage external power supplies. For example, DAC A of Fig-
ure 24 is configured to swing from –5 V to +5 V. The actual
output voltage is given by:
V
OUT
= 1+
R
F
R
S
×
D
256
×5V
()
–5V
Where D is the DAC input value (i.e., 0 to 255). This circuit
can be combined with the “fine/coarse” circuit of Figure 23 if,
for example, a very accurate adjustment around 0 V is desired.
A
V
DD
V
REFH
GND
V
REFL
AD8801/
AD8803
B
+5V
+12V
–5V
OP191
OP193
R
F
100k
R
S
100k
–5V TO +4.98V
0V TO +10V
100k
100k
+5V
Figure 24. Increasing Output Voltage Swing
DAC B of Figure 24 is in a noninverting gain of two configura-
tion, which increases the available output swing to +10 V. The
feedback resistors can be adjusted to provide any scaling of the
output voltage, within the limits of the external op amp power
supplies.
Microcomputer Interfaces
The AD8801/AD8803 serial data input provides an easy inter-
face to a variety of single-chip microcomputers (µCs). Many µCs
have a built-in serial data capability that can be used for com-
municating with the DAC. In cases where no serial port is pro-
vided, or it is being used for some other purpose (such as an
RS-232 communications interface), the AD8801/AD8803 can
easily be addressed in software.
Eleven data bits are required to load a value into the AD8801/
AD8803 (3 bits for the DAC address and 8 bits for the DAC
value). If more than 11 bits are transmitted before the Chip Se-
lect input goes high, the extra (i.e., the most-significant) bits are
ignored. This feature is valuable because most µCs only transmit
data in 8-bit increments. Thus, the µC will send 16 bits to the
DAC instead of 11 bits. The AD8801/AD8803 will only re-
spond to the last 11 bits clocked into the SDI input, however, so
the serial data interface is not affected.
An 8051 µC Interface
A typical interface between the AD8801/AD8803 and an 8051
µC is shown in Figure 25. This interface uses the 8051’s internal
serial port. The serial port is programmed for Mode 0 opera-
tion, which functions as a simple 8-bit shift register. The 8051’s
Port3.0 pin functions as the serial data output, while Port3.1
serves as the serial clock.
O1
O2
O3
O4
O5
O6
O7
O8
SDI
SCLK
RESET
SHDN
CS
V
DD
V
REFH
GND
AD8801
+5V
P3.0
P3.1
P1.3
P1.2
P1.1
SERIAL DATA SHIFT REGISTER
RxD
TxD
SHIFT CLOCK
1.11.21.3
PORT 1
SBUF
8051 µC
0.1µF 10µF
+
Figure 25. Interfacing the 8051
µ
C to an AD8801/AD8803,
Using the Serial Port
When data is written to the Serial Buffer Register (SBUF, at
Special Function Register location 99
H
), the data is automati-
cally converted to serial format and clocked out via Port3.0 and
Port3.1. After 8 bits have been transmitted, the Transmit Inter-
rupt flag (SCON.1) is set and the next 8 bits can be transmitted.
The AD8801 and AD8803 require the Chip Select to go low at
the beginning of the serial data transfer. In addition, the SCLK
input must be high when the Chip Select input goes high at the
end of the transfer. The 8051’s serial clock meets this require-
ment, since Port3.1 both begins and ends the serial data in the
high state.
Software for the 8051 Interface
A software routine for the AD8801/AD8803 to 8051 interface is
shown in Listing 1. The routine transfers the 8-bit data stored at
data memory location DAC_VALUE to the AD8801/AD8803
DAC addressed by the contents of location DAC_ADDR.

AD8803ARZ-REEL

Mfr. #:
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Description:
Digital to Analog Converters - DAC Octal 8-Bit w/ Power Shutdown
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