Si3452/3
Rev. 0.47 19
5.5. Command and Return Registers (Registers 0x12–0x1C)
The global command register enables manual port turn-on or turn-off, chip reset, port reset, and measurement of
port current and V
EE
. Register 0x12 is a Write only register. See Table 24 on page 23 for a list of all available
commands.
If the command results in a numerical return value, that value is stored in the measurement registers, which are
read-only. Each of the five possible measurements results in a 2 byte return value, and that value is stored in a
unique register. V
EE
is encoded in mV units; so, the full scale is 65.535 V. Iport is encoded in 100 µA units; so, the
full scale is 6.5535 A.
The output data is updated by the proper command register write operation (see Table 23). This means that the
numerical value of the port current or V
EE
voltage in the measurement register will be the value at the time the
command was issued. If the port turns off due to an overload or disconnect, the port current register contents will
not be set to zero. If a command to read port current is issued and the port is off, the return value will be zero.
5.6. Device Status Register (0x1D)
The device event bits are listed in Table 18.
The Device status register is RO. The V
EE
, UVLO, and overtemp bits reflect the device status. They are set if V
EE
or temperature is out of range and reset if the V
EE
or temperature is in range. Bit 6 of the Interrupt register is set if
there is a change in the overtemp status (bit 6 of 0x1D), and bit 5 of the Interrupt register is set if there is a change
in the V
EE
UVLO status (bit 5 of 0x1D). Reading register 0x1D clears these bits of the Interrupt register but does
not clear the device status register.
In addition, bit B0 indicates whether or not detection back-off is used. For PSEs that are wired as Alternative B
(power on the spare pair–typically used for midspans), the time between detection pulses is increased to slightly
over two seconds to avoid interference with Alternative A (power on the data pair–typically used for endpoints). Bit
B0 can be toggled using the 0x10 command code.
Table 18. Device Status Bits
Bit Description
B6 - OverTemp
The Si3452/3 has per-port thermal shutdown sensors as well a global thermal shutdown
at a slightly higher temperature. The global thermal shutdown bit of the device event
register is set if this occurs.
B5 - V
EE
UVLO
V
EE
UVLO. The part is put in its reset state if V
EE
is not in a valid range.
Si3452/3
20 Rev. 0.47
Table 19. Si3452/3 Register Map
Address Register Name Type B7 B6 B5 B4 B3 B2 B1 B0 POWER_UP
Interrupts
0x00 Interrupt Reg 1 RO
Overtemp
change
V
EE
UVLO
change
Port 4 event Port 3 event Port 2 event Port 1 event 0x00
0x01 Interrupt Mask 1 RW
Device sta-
tus mask
t
START
mask tI
CUT
mask Rgood CLS mask DET compl mask
Disconnect
mask
PwrGood mask PwrEn mask 0x85
Port Events
0x02 Port 1 Events COR t
START
Event tI
CUT
Event Rgood CLS DET compl Disconnect Ev
PwrGood
Change
PwrEn
Change
0x00
0x03 Port 2 Events COR t
START
Event tI
CUT
Event Rgood CLS DET compl Disconnect Ev
PwrGood
Change
PwrEn
Change
0x00
0x04 Port 3 Events COR t
START
Event tI
CUT
Event Rgood CLS DET compl Disconnect Ev
PwrGood
Change
PwrEn
Change
0x00
0x05 Port 4 Events COR t
START
Event tI
CUT
Event Rgood CLS DET compl Disconnect Ev
PwrGood
Change
PwrEn
Change
0x00
Status
0x06 Port 1 Status RO
PwrGood
Status
PwrEnable
Status
CLS Stat B2 CLS Stat B1 CLS Stat B0 DET Stat B2 DET Stat B1 DET Stat B0 0x00
0x07 Port 2 Status RO
PwrGood
Status
PwrEnable
Status
CLS Stat B2 CLS Stat B1 CLS Stat B0 DET Stat B2 DET Stat B1 DET Stat B0 0x00
0x08 Port 3 Status RO
PwrGood
Status
PwrEnable
Status
CLS Stat B2 CLS Stat B1 CLS Stat B0 DET Stat B2 DET Stat B1 DET Stat B0 0x00
0x09 Port 4 Status RO
PwrGood
Status
PwrEnable
Status
CLS Stat B2 CLS Stat B1 CLS Stat B0 DET Stat B2 DET Stat B1 DET Stat B0 0x00
Configuration
0x0A Port 1 Config RW Port priority PoE+ Discon En Port Mode B1 Port Mode B0 00000100b
0x0B Port 2 Config RW Port priority PoE+ Discon En Port Mode B1 Port Mode B0 00000100b
0x0C Port 3 Config RW Port priority PoE+ Discon En Port Mode B1 Port Mode B0 00000100b
0x0D Port 4 Config RW Port priority PoE+ Discon En Port Mode B1 Port Mode B0 00000100b
0x0E Port 1 I
CUT
RW B7 B6 B5 B4 B3 B2 B1 B0 0x75
0x0F Port 2 I
CUT
RW B7 B6 B5 B4 B3 B2 B1 B0 0x75
0x10 Port 3 I
CUT
RW B7 B6 B5 B4 B3 B2 B1 B0 0x75
0x11 Port 4 I
CUT
RW B7 B6 B5 B4 B3 B2 B1 B0 0x75
Si3452/3
Rev. 0.47 21
Global Device
0x12
Command Reg-
ister
WO CMD Code B5 CMD Code B4 CMD Code B3 CMD Code B2
CMD Param
B1
CMD Param
B0
0x00
0x13 V
EE
MSB RO 0x00
0x14 V
EE
LSB RO 0x00
0x15
Current P1
MSB
RO 0x00
0x16 Current P1 LSB RO 0x00
0x17
Current P2
MSB
RO 0x00
0x18 Current P2 LSB RO 0x00
0x19
Current P3
MSB
RO 0x00
0x1A Current P3 LSB RO 0x00
0x1B
Current P4
MSB
RO 0x00
0x1C Current P4 LSB RO 0x00
0x1D Device Status RO OverTemp V
EE
UVLO
Alternative B
Timing
0x00
Revision
0x60
Hardware
Revision
RO
0x61
Firmware Revi-
sion
RO
0x62
Firmware Revi-
sion
RO
0x63
Firmware Revi-
sion
RO
Table 19. Si3452/3 Register Map (Continued)
Address Register Name Type B7 B6 B5 B4 B3 B2 B1 B0 POWER_UP

SI3452-B01-GM

Mfr. #:
Manufacturer:
Silicon Labs
Description:
Hot Swap Voltage Controllers Quad PoE/PoE+ PSE port controller (dV/dt disconnect)
Lifecycle:
New from this manufacturer.
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