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SI3452-B01-GM

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36
Si3452/3
Rev. 0.47 7
Table 6. VOUT Drive and Power-on Specifications
Description
Symbol Test Conditions Min Typ Max Unit
Max output resistance
(port on)
R
ON
I
Port
≤ 720 mA — 0.3 0.6 Ω
Current limit
I
LIM
1x mode, V
port
=V
EE
+ 1 V 400 425 450 mA
Change in current limit I
LIM
1x mode, V
port
=V
EE
+ 1V to –30V
1
–2 — 2 %
Current limit
I
LIM
2x mode, V
port
=V
EE
+ 1 V 800 860 920 mA
Change in current limit I
LIM
2x mode, V
port
=V
EE
+ 1V to –40V
2
–2 — 2 %
Current limit I
LIM
1x mode or 2x mode, V
port
=–10V 60 — — mA
Overload current
threshold
I
CUT
Class 0
Class 1 (class policing enabled)
3
Class 2 (class policing enabled)
3
Class 3
Class 4
4
350
91
160
350
600
—
—
—
—
—
—
—
—
—
—
mA
Over current time limit
5
T
OVLD
Load current ≥ I
CUT
or I
LIM
50 — 75 ms
VOUTn turn-on slew T
RISE
10% to 90% 15 70 — µs
Power turn on timing T
PON
Time from end of valid detect to
power on
——400ms
VOUTn leakage current I
OUT_LEAK
Port in shutdown — — 10 µA
Notes:
1. T
J
>25 °C, –35 V over the full temperature range.
2. 1x mode current limit is enforced during the 60 ms T
START
time.
3. In auto mode, class policing is automatically enabled. In manual mode, I
CUT
must be programmed manually.
See "5.4. Port Configuration (Registers 0x0A–0x11)" on page 18 for more information.
4. 600 mA is consistent with the IEEE 802.3at draft standard. I
CUT
is user-programmable in 3.2 mA increments to over
800 mA for non-standard applications.
5. For 2x mode and extreme overload or short-circuit events, T
OVLD
will dynamically decrease to prevent excessive FET
heating. This is consistent with the 802.3at draft.
Table 7. DC- and dV/dt Disconnect Specifications
Description Symbol Test Conditions Min Typ Max Unit
Load current to prevent
disconnect
I
ON
10 — — mA
Load current to
guarantee disconnect
I
OFF
dc disconnect — — 5 mA
dV/dt disconnect — — 2 mA
Disconnect delay T
DCDV_DLY
Time from I
OFF
load current to port
turn off
300 — 400 ms
Si3452/3
8 Rev. 0.47
Table 8. Port Measurement and Monitoring Specifications
Description Symbol Test Conditions Min Typ Max Unit
Port current measurement
offset
I
OFFSET
20 mA ≤ I
PORT
≤ I
CUT
. For final
I
PORT
reading, add offset to % of
reading tolerance.
–5 — 5 mA
Port current measurement
tolerance
%
TOL
–4 — 4 %
Table 9. SMBus (I
2
C) Electrical Specifications
VDD = 3.0 to 3.6 V
Description Symbol Test Conditions Min Typ Max Unit
Input low voltage
V
IL
SCL, SDA pins T
j
< –10 °C — — 0.85 V
SCL, SDA pins over full temp range 0.8
Input high voltage V
IH
SCL, SDA pins 2.2 — — V
Output low voltage V
OL
SCL, SDA pins,
driving ≤ 8.5 mA
——0.6V
Input leakage current I
L
SCL, SDA pins — — 40 µA
Table 10. Address Pin Electrical Specifications*
VDD = 3.0 to 3.6 V
Description Symbol Test Conditions Min Typ Max Unit
Input low voltage V
IL
AD0, AD1, AD2, AD3 pins — — 0.8 V
Input high voltage V
IH
AD0, AD1, AD2, AD3 pins 0.7 x V
DD
——V
Input leakage current I
H
, I
L
AD0, AD1, AD2, AD3 pins –10 — 10 µA
*Note: At power-up, these pins are logic inputs. A 10 k pull up or pull down resistor is used for address selection. After
address recognition, the pins are used for internal communications.
Si3452/3
Rev. 0.47 9
Table 11. SMBus (I
2
C) Timing Specifications (see Figure 1)
VDD = 3.0 to 3.6 V
Description Symbol Test Conditions Min Typ Max Unit
Serial bus clock frequency f
SCL
0—400kHz
SCL high time t
SKH
600 — — ns
SCL low time t
SKL
1.3 — — μs
SCL, SDA rise time t
R_SCL
20 — 300 ns
SCL, SDA fall time t
F_SCL
20 — 150 ns
Bus free time t
BUF
Between START and STOP
conditions.
1.3 — — μs
Start hold time t
STH
Between START and first low SCL. 600 — — ns
Start setup time t
STS
Between SCL high and START
condition.
600 — — ns
Stop setup time t
SPS
Between SCL high and STOP
condition.
600 — — ns
Data hold time t
DH
200 — — ns
Data setup time t
DS
200 — — ns
Time from hardware or soft-
ware reset until start of I
2
C
traffic
t
RESET
Reset to start condition — — 100 ms
Delay from event to INT pin
low or from clear-on-read to
INT pin high
t
INT
—— 5ms
Notes:
1. Not production tested (guaranteed by design).
2. All timing references measured at V
IL
and V
IH
.
3. The Si3452/3 will stretch (pull down on) SCK during the ACK time period if required. The maximum SCL stretching is
10 µsec; so, SCL only needs to be bidirectional for I
2
C bus speeds over 50 kHz.
SCL
D7
fSC L
tR_SCL tF_SCL tSK H
SDA
tSKL
tST H tSPS
D6 D5 D4 D3 D0
tDS tDH
Start Bit Stop Bit
tBUF
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SI3452-B01-GM

Mfr. #:
Buy SI3452-B01-GM
Manufacturer:
Silicon Labs
Description:
Hot Swap Voltage Controllers Quad PoE/PoE+ PSE port controller (dV/dt disconnect)
Lifecycle:
New from this manufacturer.
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