Si3452/3
Rev. 0.47 25
7. PCB Layout Guidelines
Following are some PCB layout considerations. See also "12.1. Evaluation Kits and Reference Designs" on page
33 for reference design information. Please visit the Silicon Labs technical support web page at
https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to request support for your
design, particularly if you are not closely following the recommended reference design.
Due to the high current of up to 800 mA per port, the following board layout guidelines apply. In addition, contact
Silicon Laboratories for access to complete PSE reference design databases including recommended layouts.
The VEE1, VEE2, VEE3, and VEE4 pins can carry up to 800 mA and are connected to a V
EE
bus. The V
EE
bus for
a 24 port PCB layout can thus carry as much as 20 A current. With 2 oz. copper on an outer layer, a bus of 0.4
inches is needed. For an inner layer, this increases to a 1 inch wide bus. Use of large or multiple vias is required for
properly supporting the 800 mA per channel operating current. The VEE pin does not carry high current and can be
connected directly to the bus as well. The best practice is to devote an entire inner layer for V
EE
power routing.
Similarly, GND1/2 and GND3/4 pins can carry up to 1.6 A per pin, and the GND return bus should be at least as
wide as the V
EE
bus described above. The best practice is to devote an entire inner layer for ground power routing.
The ground power plane does not generally have a high frequency content (other than external faults); so, it is
generally acceptable to use the ground power plane as a ground signal plane and tie AGND and GND12, GND34
to this plane as well.
The VOUTn pins carry up to 800 mA dc and up to 5 A in faults; so, a 20 mil trace with wide or multiple vias is also
recommended. The VDETn pins also carry fault current; so, this pin connection to VOUTn needs to use 20 mil
traces and wide or multiple vias where needed.
The VDD currents are not large; so, it is acceptable to route the VDD nodes on one of the outer layers.
If care is taken to avoid disruption of the high current paths, VDD can be globally routed on one of the power planes
and then locally routed on an inner or outer layer.
To avoid coupling between surge events and logic signals, it is recommended that VOUTn traces be routed on the
side opposite the I
2
C interface pins.
The thermal pad of the Si3452/3 is connected to VEE. At full IEEE 802.3at current of 600 mA on each port, the
dissipation of the Si3452/3 is up to 1.2 W; so, multiple vias are required to conduct the heat from the thermal pad to
the VEE plane. As many as 36 small vias provide the best thermal conduction.
